/[gxemul]/trunk/src/include/cpu_sh.h
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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revision 18 by dpavlin, Mon Oct 8 16:19:11 2007 UTC revision 30 by dpavlin, Mon Oct 8 16:20:40 2007 UTC
# Line 2  Line 2 
2  #define CPU_SH_H  #define CPU_SH_H
3    
4  /*  /*
5   *  Copyright (C) 2005  Anders Gavare.  All rights reserved.   *  Copyright (C) 2005-2006  Anders Gavare.  All rights reserved.
6   *   *
7   *  Redistribution and use in source and binary forms, with or without   *  Redistribution and use in source and binary forms, with or without
8   *  modification, are permitted provided that the following conditions are met:   *  modification, are permitted provided that the following conditions are met:
# Line 28  Line 28 
28   *  SUCH DAMAGE.   *  SUCH DAMAGE.
29   *   *
30   *   *
31   *  $Id: cpu_sh.h,v 1.7 2005/10/27 14:01:15 debug Exp $   *  $Id: cpu_sh.h,v 1.21 2006/07/25 21:49:14 debug Exp $
32   */   */
33    
34  #include "misc.h"  #include "misc.h"
# Line 36  Line 36 
36    
37  struct cpu_family;  struct cpu_family;
38    
39    /*  SH CPU types:  */
40    struct sh_cpu_type_def {
41            char            *name;
42            int             bits;
43    };
44    
45    #define SH_CPU_TYPE_DEFS        {       \
46            { "SH3", 32 },                  \
47            { "SH4", 32 },                  \
48            { "SH5", 64 },                  \
49            { NULL, 0 } }
50    
51  #define SH_N_IC_ARGS                    3  
52  #define SH_INSTR_ALIGNMENT_SHIFT        2  /*
53  #define SH_IC_ENTRIES_SHIFT             10   *  TODO: Figure out how to nicely support multiple instruction encodings!
54     *  For now, I'm reverting this to SH4. SH5 will have to wait until later.
55     */
56    
57    #define SH_N_IC_ARGS                    2       /*  3 for SH5/SH64  */
58    #define SH_INSTR_ALIGNMENT_SHIFT        1       /*  2 for SH5/SH64  */
59    #define SH_IC_ENTRIES_SHIFT             11      /*  10 for SH5/SH64  */
60  #define SH_IC_ENTRIES_PER_PAGE          (1 << SH_IC_ENTRIES_SHIFT)  #define SH_IC_ENTRIES_PER_PAGE          (1 << SH_IC_ENTRIES_SHIFT)
61  #define SH_PC_TO_IC_ENTRY(a)            (((a)>>SH_INSTR_ALIGNMENT_SHIFT) \  #define SH_PC_TO_IC_ENTRY(a)            (((a)>>SH_INSTR_ALIGNMENT_SHIFT) \
62                                          & (SH_IC_ENTRIES_PER_PAGE-1))                                          & (SH_IC_ENTRIES_PER_PAGE-1))
63  #define SH_ADDR_TO_PAGENR(a)            ((a) >> (SH_IC_ENTRIES_SHIFT \  #define SH_ADDR_TO_PAGENR(a)            ((a) >> (SH_IC_ENTRIES_SHIFT \
64                                          + SH_INSTR_ALIGNMENT_SHIFT))                                          + SH_INSTR_ALIGNMENT_SHIFT))
65    
66  struct sh_instr_call {  #define SH_L2N          17
67          void    (*f)(struct cpu *, struct sh_instr_call *);  #define SH_L3N          18
         size_t  arg[SH_N_IC_ARGS];  
 };  
68    
69  /*  Translation cache struct for each physical page:  */  DYNTRANS_MISC_DECLARATIONS(sh,SH,uint64_t)
70  struct sh_tc_physpage {  DYNTRANS_MISC64_DECLARATIONS(sh,SH,uint8_t)
         struct sh_instr_call ics[SH_IC_ENTRIES_PER_PAGE + 1];  
         uint32_t        next_ofs;       /*  or 0 for end of chain  */  
         int             flags;  
         uint64_t        physaddr;  
 };  
71    
72  #define SH_N_VPH_ENTRIES                1048576  #define SH_MAX_VPH_TLB_ENTRIES          128
73    
74    
75    #define SH_N_GPRS               64
76    
 #define SH_MAX_VPH_TLB_ENTRIES          256  
 struct sh_vpg_tlb_entry {  
         int             valid;  
         int             writeflag;  
         int64_t         timestamp;  
         unsigned char   *host_page;  
         uint64_t        vaddr_page;  
         uint64_t        paddr_page;  
 };  
77    
78  struct sh_cpu {  struct sh_cpu {
79          int             bits;          struct sh_cpu_type_def cpu_type;
         int             compact;  
80    
81          uint64_t        r[64];          /*  compact = 1 if currently executing 16-bit long opcodes  */
82            int             compact;
83    
84            uint32_t        r_otherbank[8];
85    
86          /*          uint64_t        r[SH_N_GPRS];
          *  Instruction translation cache:  
          */  
87    
88          /*  cur_ic_page is a pointer to an array of SH_IC_ENTRIES_PER_PAGE          uint32_t        mach;           /*  Multiply-Accumulate High  */
89              instruction call entries. next_ic points to the next such          uint32_t        macl;           /*  Multiply-Accumulate Low  */
90              call to be executed.  */          uint32_t        pr;             /*  Procedure Register  */
91          struct sh_tc_physpage   *cur_physpage;          uint32_t        fpscr;          /*  Floating-point Status/Control  */
92          struct sh_instr_call    *cur_ic_page;          uint32_t        fpul;           /*  Floating-point Communication Reg  */
93          struct sh_instr_call    *next_ic;          uint32_t        sr;             /*  Status Register  */
94            uint32_t        ssr;            /*  Saved Status Register  */
95            uint32_t        spc;            /*  Saved PC  */
96            uint32_t        gbr;            /*  Global Base Register  */
97            uint32_t        vbr;            /*  Vector Base Register  */
98            uint32_t        sgr;            /*  Saved General Register  */
99            uint32_t        dbr;            /*  Debug Base Register  */
100    
101    
102          /*          /*
103           *  Virtual -> physical -> host address translation:           *  Instruction translation cache and Virtual->Physical->Host
104           *           *  address translation:
          *  host_load and host_store point to arrays of SH_N_VPH_ENTRIES  
          *  pointers (to host pages); phys_addr points to an array of  
          *  SH_N_VPH_ENTRIES uint32_t.  
105           */           */
106            DYNTRANS_ITC(sh)
107            VPH_TLBS(sh,SH)
108            VPH32(sh,SH,uint64_t,uint8_t)
109            VPH64(sh,SH,uint8_t)
110    };
111    
         struct sh_vpg_tlb_entry  vph_tlb_entry[SH_MAX_VPH_TLB_ENTRIES];  
         unsigned char            *host_load[SH_N_VPH_ENTRIES];  
         unsigned char            *host_store[SH_N_VPH_ENTRIES];  
         uint32_t                 phys_addr[SH_N_VPH_ENTRIES];  
         struct sh_tc_physpage    *phys_page[SH_N_VPH_ENTRIES];  
112    
113          uint32_t                 phystranslation[SH_N_VPH_ENTRIES/32];  /*  Status register bits:  */
114  };  #define SH_SR_T                 0x00000001      /*  True/false  */
115    #define SH_SR_S                 0x00000002      /*  Saturation  */
116    #define SH_SR_IMASK             0x000000f0      /*  Interrupt mask  */
117    #define SH_SR_IMASK_SHIFT               4
118    #define SH_SR_Q                 0x00000100      /*  State for Divide Step  */
119    #define SH_SR_M                 0x00000200      /*  State for Divide Step  */
120    #define SH_SR_FD                0x00008000      /*  FPU Disable  */
121    #define SH_SR_BL                0x10000000      /*  Exception/Interrupt Block */
122    #define SH_SR_RB                0x20000000      /*  Register Bank 0/1  */
123    #define SH_SR_MD                0x40000000      /*  Privileged Mode  */
124    
125    
126  /*  cpu_sh.c:  */  /*  cpu_sh.c:  */
127    int sh_run_instr(struct cpu *cpu);
128  void sh_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,  void sh_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
129          unsigned char *host_page, int writeflag, uint64_t paddr_page);          unsigned char *host_page, int writeflag, uint64_t paddr_page);
130  void sh_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);  void sh_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
131  void sh_invalidate_code_translation(struct cpu *cpu, uint64_t, int);  void sh_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
132    int sh32_run_instr(struct cpu *cpu);
133  void sh32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,  void sh32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
134          unsigned char *host_page, int writeflag, uint64_t paddr_page);          unsigned char *host_page, int writeflag, uint64_t paddr_page);
135  void sh32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);  void sh32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
136  void sh32_invalidate_code_translation(struct cpu *cpu, uint64_t, int);  void sh32_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
137    void sh_init_64bit_dummy_tables(struct cpu *cpu);
138  int sh_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,  int sh_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
139          unsigned char *data, size_t len, int writeflag, int cache_flags);          unsigned char *data, size_t len, int writeflag, int cache_flags);
140  int sh_cpu_family_init(struct cpu_family *);  int sh_cpu_family_init(struct cpu_family *);
141    
142    void sh_update_sr(struct cpu *cpu, uint32_t new_sr);
143    
144    /*  memory_sh.c:  */
145    int sh_translate_v2p(struct cpu *cpu, uint64_t vaddr,
146            uint64_t *return_addr, int flags);
147    
148    
149  #endif  /*  CPU_SH_H  */  #endif  /*  CPU_SH_H  */
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