src/include/cpu_sh.h

#ifndef CPU_SH_H
#define CPU_SH_H

/*
 *  Copyright (C) 2005-2006  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *
 *
 *  $Id: cpu_sh.h,v 1.21 2006/07/25 21:49:14 debug Exp $
 */

#include "misc.h"


struct cpu_family;

/*  SH CPU types:  */
struct sh_cpu_type_def {
        char            *name;
        int             bits;
};

#define SH_CPU_TYPE_DEFS        {       \
        { "SH3", 32 },                  \
        { "SH4", 32 },                  \
        { "SH5", 64 },                  \
        { NULL, 0 } }


/*
 *  TODO: Figure out how to nicely support multiple instruction encodings!
 *  For now, I'm reverting this to SH4. SH5 will have to wait until later.
 */

#define SH_N_IC_ARGS                    2       /*  3 for SH5/SH64  */
#define SH_INSTR_ALIGNMENT_SHIFT        1       /*  2 for SH5/SH64  */
#define SH_IC_ENTRIES_SHIFT             11      /*  10 for SH5/SH64  */
#define SH_IC_ENTRIES_PER_PAGE          (1 << SH_IC_ENTRIES_SHIFT)
#define SH_PC_TO_IC_ENTRY(a)            (((a)>>SH_INSTR_ALIGNMENT_SHIFT) \
                                        & (SH_IC_ENTRIES_PER_PAGE-1))
#define SH_ADDR_TO_PAGENR(a)            ((a) >> (SH_IC_ENTRIES_SHIFT \
                                        + SH_INSTR_ALIGNMENT_SHIFT))

#define SH_L2N          17
#define SH_L3N          18

DYNTRANS_MISC_DECLARATIONS(sh,SH,uint64_t)
DYNTRANS_MISC64_DECLARATIONS(sh,SH,uint8_t)

#define SH_MAX_VPH_TLB_ENTRIES          128


#define SH_N_GPRS               64


struct sh_cpu {
        struct sh_cpu_type_def cpu_type;

        /*  compact = 1 if currently executing 16-bit long opcodes  */
        int             compact;

        uint32_t        r_otherbank[8];

        uint64_t        r[SH_N_GPRS];

        uint32_t        mach;           /*  Multiply-Accumulate High  */
        uint32_t        macl;           /*  Multiply-Accumulate Low  */
        uint32_t        pr;             /*  Procedure Register  */
        uint32_t        fpscr;          /*  Floating-point Status/Control  */
        uint32_t        fpul;           /*  Floating-point Communication Reg  */
        uint32_t        sr;             /*  Status Register  */
        uint32_t        ssr;            /*  Saved Status Register  */
        uint32_t        spc;            /*  Saved PC  */
        uint32_t        gbr;            /*  Global Base Register  */
        uint32_t        vbr;            /*  Vector Base Register  */
        uint32_t        sgr;            /*  Saved General Register  */
        uint32_t        dbr;            /*  Debug Base Register  */


        /*
         *  Instruction translation cache and Virtual->Physical->Host
         *  address translation:
         */
        DYNTRANS_ITC(sh)
        VPH_TLBS(sh,SH)
        VPH32(sh,SH,uint64_t,uint8_t)
        VPH64(sh,SH,uint8_t)
};


/*  Status register bits:  */
#define SH_SR_T                 0x00000001      /*  True/false  */
#define SH_SR_S                 0x00000002      /*  Saturation  */
#define SH_SR_IMASK             0x000000f0      /*  Interrupt mask  */
#define SH_SR_IMASK_SHIFT               4
#define SH_SR_Q                 0x00000100      /*  State for Divide Step  */
#define SH_SR_M                 0x00000200      /*  State for Divide Step  */
#define SH_SR_FD                0x00008000      /*  FPU Disable  */
#define SH_SR_BL                0x10000000      /*  Exception/Interrupt Block */
#define SH_SR_RB                0x20000000      /*  Register Bank 0/1  */
#define SH_SR_MD                0x40000000      /*  Privileged Mode  */


/*  cpu_sh.c:  */
int sh_run_instr(struct cpu *cpu);
void sh_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
        unsigned char *host_page, int writeflag, uint64_t paddr_page);
void sh_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
void sh_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
int sh32_run_instr(struct cpu *cpu);
void sh32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
        unsigned char *host_page, int writeflag, uint64_t paddr_page);
void sh32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
void sh32_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
void sh_init_64bit_dummy_tables(struct cpu *cpu);
int sh_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
        unsigned char *data, size_t len, int writeflag, int cache_flags);
int sh_cpu_family_init(struct cpu_family *);

void sh_update_sr(struct cpu *cpu, uint32_t new_sr);

/*  memory_sh.c:  */
int sh_translate_v2p(struct cpu *cpu, uint64_t vaddr,
        uint64_t *return_addr, int flags);


#endif  /*  CPU_SH_H  */
1	dpavlin	14	#ifndef CPU_SH_H
2			#define CPU_SH_H
3
4			/*
5	dpavlin	22	* Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
6	dpavlin	14	*
7			* Redistribution and use in source and binary forms, with or without
8			* modification, are permitted provided that the following conditions are met:
9			*
10			* 1. Redistributions of source code must retain the above copyright
11			* notice, this list of conditions and the following disclaimer.
12			* 2. Redistributions in binary form must reproduce the above copyright
13			* notice, this list of conditions and the following disclaimer in the
14			* documentation and/or other materials provided with the distribution.
15			* 3. The name of the author may not be used to endorse or promote products
16			* derived from this software without specific prior written permission.
17			*
18			* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19			* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20			* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21			* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22			* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23			* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24			* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25			* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26			* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27			* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28			* SUCH DAMAGE.
29			*
30			*
31	dpavlin	30	* $Id: cpu_sh.h,v 1.21 2006/07/25 21:49:14 debug Exp $
32	dpavlin	14	*/
33
34			#include "misc.h"
35
36
37			struct cpu_family;
38
39	dpavlin	30	/* SH CPU types: */
40			struct sh_cpu_type_def {
41			char *name;
42			int bits;
43			};
44	dpavlin	14
45	dpavlin	30	#define SH_CPU_TYPE_DEFS { \
46			{ "SH3", 32 }, \
47			{ "SH4", 32 }, \
48			{ "SH5", 64 }, \
49			{ NULL, 0 } }
50
51
52			/*
53			* TODO: Figure out how to nicely support multiple instruction encodings!
54			* For now, I'm reverting this to SH4. SH5 will have to wait until later.
55			*/
56
57			#define SH_N_IC_ARGS 2 /* 3 for SH5/SH64 */
58			#define SH_INSTR_ALIGNMENT_SHIFT 1 /* 2 for SH5/SH64 */
59			#define SH_IC_ENTRIES_SHIFT 11 /* 10 for SH5/SH64 */
60	dpavlin	14	#define SH_IC_ENTRIES_PER_PAGE (1 << SH_IC_ENTRIES_SHIFT)
61			#define SH_PC_TO_IC_ENTRY(a) (((a)>>SH_INSTR_ALIGNMENT_SHIFT) \
62			& (SH_IC_ENTRIES_PER_PAGE-1))
63			#define SH_ADDR_TO_PAGENR(a) ((a) >> (SH_IC_ENTRIES_SHIFT \
64			+ SH_INSTR_ALIGNMENT_SHIFT))
65
66	dpavlin	24	#define SH_L2N 17
67			#define SH_L3N 18
68
69	dpavlin	22	DYNTRANS_MISC_DECLARATIONS(sh,SH,uint64_t)
70	dpavlin	24	DYNTRANS_MISC64_DECLARATIONS(sh,SH,uint8_t)
71	dpavlin	14
72	dpavlin	22	#define SH_MAX_VPH_TLB_ENTRIES 128
73	dpavlin	14
74
75	dpavlin	30	#define SH_N_GPRS 64
76
77
78	dpavlin	14	struct sh_cpu {
79	dpavlin	30	struct sh_cpu_type_def cpu_type;
80
81			/* compact = 1 if currently executing 16-bit long opcodes */
82	dpavlin	14	int compact;
83
84	dpavlin	30	uint32_t r_otherbank[8];
85	dpavlin	14
86	dpavlin	30	uint64_t r[SH_N_GPRS];
87	dpavlin	14
88	dpavlin	30	uint32_t mach; /* Multiply-Accumulate High */
89			uint32_t macl; /* Multiply-Accumulate Low */
90			uint32_t pr; /* Procedure Register */
91			uint32_t fpscr; /* Floating-point Status/Control */
92			uint32_t fpul; /* Floating-point Communication Reg */
93			uint32_t sr; /* Status Register */
94			uint32_t ssr; /* Saved Status Register */
95			uint32_t spc; /* Saved PC */
96			uint32_t gbr; /* Global Base Register */
97			uint32_t vbr; /* Vector Base Register */
98			uint32_t sgr; /* Saved General Register */
99			uint32_t dbr; /* Debug Base Register */
100
101
102	dpavlin	14	/*
103	dpavlin	22	* Instruction translation cache and Virtual->Physical->Host
104			* address translation:
105	dpavlin	14	*/
106	dpavlin	22	DYNTRANS_ITC(sh)
107			VPH_TLBS(sh,SH)
108			VPH32(sh,SH,uint64_t,uint8_t)
109			VPH64(sh,SH,uint8_t)
110	dpavlin	14	};
111
112
113	dpavlin	30	/* Status register bits: */
114			#define SH_SR_T 0x00000001 /* True/false */
115			#define SH_SR_S 0x00000002 /* Saturation */
116			#define SH_SR_IMASK 0x000000f0 /* Interrupt mask */
117			#define SH_SR_IMASK_SHIFT 4
118			#define SH_SR_Q 0x00000100 /* State for Divide Step */
119			#define SH_SR_M 0x00000200 /* State for Divide Step */
120			#define SH_SR_FD 0x00008000 /* FPU Disable */
121			#define SH_SR_BL 0x10000000 /* Exception/Interrupt Block */
122			#define SH_SR_RB 0x20000000 /* Register Bank 0/1 */
123			#define SH_SR_MD 0x40000000 /* Privileged Mode */
124
125
126	dpavlin	14	/* cpu_sh.c: */
127	dpavlin	28	int sh_run_instr(struct cpu *cpu);
128	dpavlin	14	void sh_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
129			unsigned char *host_page, int writeflag, uint64_t paddr_page);
130	dpavlin	18	void sh_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
131	dpavlin	14	void sh_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
132	dpavlin	28	int sh32_run_instr(struct cpu *cpu);
133	dpavlin	14	void sh32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
134			unsigned char *host_page, int writeflag, uint64_t paddr_page);
135	dpavlin	18	void sh32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
136	dpavlin	14	void sh32_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
137	dpavlin	24	void sh_init_64bit_dummy_tables(struct cpu *cpu);
138	dpavlin	14	int sh_memory_rw(struct cpu cpu, struct memory mem, uint64_t vaddr,
139			unsigned char *data, size_t len, int writeflag, int cache_flags);
140			int sh_cpu_family_init(struct cpu_family *);
141
142	dpavlin	30	void sh_update_sr(struct cpu *cpu, uint32_t new_sr);
143	dpavlin	14
144	dpavlin	30	/* memory_sh.c: */
145			int sh_translate_v2p(struct cpu *cpu, uint64_t vaddr,
146			uint64_t *return_addr, int flags);
147
148
149	dpavlin	14	#endif /* CPU_SH_H */