1 |
#ifndef ARM_CPU_TYPES_H |
2 |
#define ARM_CPU_TYPES_H |
3 |
|
4 |
/* |
5 |
* Copyright (C) 2005 Anders Gavare. All rights reserved. |
6 |
* |
7 |
* Redistribution and use in source and binary forms, with or without |
8 |
* modification, are permitted provided that the following conditions are met: |
9 |
* |
10 |
* 1. Redistributions of source code must retain the above copyright |
11 |
* notice, this list of conditions and the following disclaimer. |
12 |
* 2. Redistributions in binary form must reproduce the above copyright |
13 |
* notice, this list of conditions and the following disclaimer in the |
14 |
* documentation and/or other materials provided with the distribution. |
15 |
* 3. The name of the author may not be used to endorse or promote products |
16 |
* derived from this software without specific prior written permission. |
17 |
* |
18 |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
19 |
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
20 |
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
21 |
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
22 |
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
23 |
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
24 |
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
25 |
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
26 |
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
27 |
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
28 |
* SUCH DAMAGE. |
29 |
* |
30 |
* |
31 |
* $Id: arm_cpu_types.h,v 1.4 2005/09/20 21:05:23 debug Exp $ |
32 |
*/ |
33 |
|
34 |
/* See cpu_arm.h for struct arm_cpu_type_def. */ |
35 |
/* See armreg.h for CPU_ID_xxx defines. */ |
36 |
|
37 |
/* Flags: */ |
38 |
#define ARM_NO_MMU 1 |
39 |
#define ARM_DUAL_ENDIAN 2 |
40 |
|
41 |
#include "armreg.h" |
42 |
|
43 |
/* |
44 |
* NOTE: Most of these are bogus! |
45 |
*/ |
46 |
|
47 |
#define ARM_CPU_TYPE_DEFS { \ |
48 |
{ "ARM3", CPU_ID_ARM3, ARM_DUAL_ENDIAN,12, 1, 0, 1 }, \ |
49 |
{ "ARM610", CPU_ID_ARM600, ARM_DUAL_ENDIAN,12, 1, 0, 1 }, \ |
50 |
{ "ARM610", CPU_ID_ARM610, ARM_DUAL_ENDIAN,12, 1, 0, 1 }, \ |
51 |
{ "ARM620", CPU_ID_ARM620, ARM_DUAL_ENDIAN,12, 1, 0, 1 }, \ |
52 |
\ |
53 |
{ "ARM700", CPU_ID_ARM700, 0, 12, 1, 0, 1 }, \ |
54 |
{ "ARM710", CPU_ID_ARM710, 0, 12, 1, 0, 1 }, \ |
55 |
{ "ARM710A", CPU_ID_ARM710A, 0, 12, 1, 0, 1 }, \ |
56 |
{ "ARM720T", CPU_ID_ARM720T, 0, 12, 1, 0, 1 }, \ |
57 |
{ "ARM740T4K", CPU_ID_ARM740T4K,ARM_NO_MMU, 12, 1, 0, 1 }, \ |
58 |
{ "ARM740T8K", CPU_ID_ARM740T8K,ARM_NO_MMU, 13, 1, 0, 1 }, \ |
59 |
{ "ARM7500", CPU_ID_ARM7500, 0, 12, 1, 0, 1 }, \ |
60 |
{ "ARM7500FE", CPU_ID_ARM7500FE,0, 12, 1, 0, 1 }, \ |
61 |
\ |
62 |
{ "ARM810", CPU_ID_ARM810, 0, 12, 1, 0, 1 }, \ |
63 |
{ "ARM920T", CPU_ID_ARM920T, 0, 12, 1, 0, 1 }, \ |
64 |
{ "ARM922T", CPU_ID_ARM922T, 0, 12, 1, 0, 1 }, \ |
65 |
{ "ARM940T", CPU_ID_ARM940T, ARM_NO_MMU, 12, 1, 0, 1 }, \ |
66 |
\ |
67 |
{ "ARM946ES", CPU_ID_ARM946ES,ARM_NO_MMU, 12, 1, 0, 1 }, \ |
68 |
{ "ARM966ES", CPU_ID_ARM966ES,ARM_NO_MMU, 12, 1, 0, 1 }, \ |
69 |
{ "ARM966ESR1", CPU_ID_ARM966ESR1,ARM_NO_MMU, 12, 1, 0, 1 }, \ |
70 |
\ |
71 |
{ "ARM1020E", CPU_ID_ARM1020E,0, 12, 1, 0, 1 }, \ |
72 |
{ "ARM1022ES", CPU_ID_ARM1022ES,0, 12, 1, 0, 1 }, \ |
73 |
{ "ARM1026EJS", CPU_ID_ARM1026EJS,0, 12, 1, 0, 1 }, \ |
74 |
{ "ARM1136JS", CPU_ID_ARM1136JS,0, 12, 1, 0, 1 }, \ |
75 |
{ "ARM1136JSR1",CPU_ID_ARM1136JSR1,0, 12, 1, 0, 1 }, \ |
76 |
\ |
77 |
{ "SA110", CPU_ID_SA110 | 3, 0, 14, 1, 14, 1 }, \ |
78 |
{ "SA1100", CPU_ID_SA1100, 0, 14, 1, 14, 1 }, \ |
79 |
{ "SA1110", CPU_ID_SA1110, 0, 14, 1, 14, 1 }, \ |
80 |
\ |
81 |
{ "TI925T", CPU_ID_TI925T, 0, 14, 1, 14, 1 }, \ |
82 |
{ "IXP1200", CPU_ID_IXP1200, 0, 14, 1, 14, 1 }, \ |
83 |
{ "80200", CPU_ID_80200, 0, 14, 1, 14, 1 }, \ |
84 |
\ |
85 |
{ "PXA210", CPU_ID_PXA210, 0, 16, 1, 0, 1 }, \ |
86 |
{ "PXA210A", CPU_ID_PXA210A, 0, 16, 1, 0, 1 }, \ |
87 |
{ "PXA210B", CPU_ID_PXA210B, 0, 16, 1, 0, 1 }, \ |
88 |
{ "PXA210C", CPU_ID_PXA210C, 0, 16, 1, 0, 1 }, \ |
89 |
{ "PXA250", CPU_ID_PXA250, 0, 16, 1, 0, 1 }, \ |
90 |
{ "PXA250A", CPU_ID_PXA250A, 0, 16, 1, 0, 1 }, \ |
91 |
{ "PXA250B", CPU_ID_PXA250B, 0, 16, 1, 0, 1 }, \ |
92 |
{ "PXA250C", CPU_ID_PXA250C, 0, 16, 1, 0, 1 }, \ |
93 |
{ "PXA27X", CPU_ID_PXA27X, 0, 16, 1, 0, 1 }, \ |
94 |
\ |
95 |
{ "IXP425_255", CPU_ID_IXP425_266, 0, 14, 1, 14, 1 }, \ |
96 |
{ "IXP425_400", CPU_ID_IXP425_400, 0, 14, 1, 14, 1 }, \ |
97 |
{ "IXP425_533", CPU_ID_IXP425_533, 0, 14, 1, 14, 1 }, \ |
98 |
\ |
99 |
{ "80219_400", CPU_ID_80219_400,0, 14, 1, 14, 1 }, \ |
100 |
{ "80219_600", CPU_ID_80219_600,0, 14, 1, 14, 1 }, \ |
101 |
{ "80321_400", CPU_ID_80321_400,0, 14, 1, 14, 1 }, \ |
102 |
{ "80321_400_B0",CPU_ID_80321_400_B0,0, 14, 1, 14, 1 }, \ |
103 |
{ "80321_600", CPU_ID_80321_600,0, 14, 1, 14, 1 }, \ |
104 |
{ "80321_600_B0",CPU_ID_80321_600_B0,0, 14, 1, 14, 1 }, \ |
105 |
\ |
106 |
{ NULL, 0, 0, 0,0, 0,0 } } |
107 |
|
108 |
#endif /* ARM_CPU_TYPES_H */ |