src/cpus/cpu_arm_coproc.c

/*
 *  Copyright (C) 2005  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *
 *
 *  $Id: cpu_arm_coproc.c,v 1.10 2005/10/07 22:10:51 debug Exp $
 *
 *  ARM coprocessor emulation.
 */

#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <ctype.h>

#include "cpu.h"
#include "misc.h"
#include "symbol.h"


/*
 *  arm_coproc_15():
 *
 *  The system control coprocessor.
 */
void arm_coproc_15(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
        int crn, int crm, int rd)
{
        uint32_t old_control;

        /*  Some sanity checks:  */
        if (opcode1 != 0) {
                fatal("arm_coproc_15: opcode1 = %i, should be 0\n", opcode1);
                exit(1);
        }
        if (rd == ARM_PC) {
                fatal("arm_coproc_15: rd = PC\n");
                exit(1);
        }

        switch (crn) {

        case 0: /*  Main ID register:  */
                if (opcode2 != 0)
                        fatal("[ arm_coproc_15: TODO: cr0, opcode2=%i ]\n",
                            opcode2);
                if (l_bit)
                        cpu->cd.arm.r[rd] = cpu->cd.arm.cpu_type.cpu_id;
                else
                        fatal("[ arm_coproc_15: attempt to write to cr0? ]\n");
                break;

        case 1: /*  Control Register:  */
                if (l_bit) {
                        cpu->cd.arm.r[rd] = cpu->cd.arm.control;
                        return;
                }
                /*
                 *  Write to control:  Check each bit individually:
                 */
                old_control = cpu->cd.arm.control;
                cpu->cd.arm.control = cpu->cd.arm.r[rd];
                if ((old_control & ARM_CONTROL_MMU) !=
                    (cpu->cd.arm.control & ARM_CONTROL_MMU))
                        debug("[ %s the MMU ]\n", cpu->cd.arm.control &
                            ARM_CONTROL_MMU? "enabling" : "disabling");
                if ((old_control & ARM_CONTROL_ALIGN) !=
                    (cpu->cd.arm.control & ARM_CONTROL_ALIGN))
                        debug("[ %s alignment checks ]\n", cpu->cd.arm.control &
                            ARM_CONTROL_ALIGN? "enabling" : "disabling");
                if ((old_control & ARM_CONTROL_CACHE) !=
                    (cpu->cd.arm.control & ARM_CONTROL_CACHE))
                        debug("[ %s the [data] cache ]\n", cpu->cd.arm.control &
                            ARM_CONTROL_CACHE? "enabling" : "disabling");
                if ((old_control & ARM_CONTROL_WBUFFER) !=
                    (cpu->cd.arm.control & ARM_CONTROL_WBUFFER))
                        debug("[ %s the write buffer ]\n", cpu->cd.arm.control &
                            ARM_CONTROL_WBUFFER? "enabling" : "disabling");
                if ((old_control & ARM_CONTROL_BIG) !=
                    (cpu->cd.arm.control & ARM_CONTROL_BIG)) {
                        fatal("ERROR: Trying to switch endianness. Not "
                            "supported yet.\n");
                        exit(1);
                }
                if ((old_control & ARM_CONTROL_ICACHE) !=
                    (cpu->cd.arm.control & ARM_CONTROL_ICACHE))
                        debug("[ %s the icache ]\n", cpu->cd.arm.control &
                            ARM_CONTROL_ICACHE? "enabling" : "disabling");
                /*  TODO: More bits.  */
                break;

        case 2: /*  Translation Table Base register:  */
                /*  NOTE: 16 KB aligned.  */
                if (l_bit)
                        cpu->cd.arm.r[rd] = cpu->cd.arm.ttb & 0xffffc000;
                else {
                        cpu->cd.arm.ttb = cpu->cd.arm.r[rd];
                        if (cpu->cd.arm.ttb & 0x3fff)
                                fatal("[ WARNING! low bits of new TTB non-"
                                    "zero? 0x%08x ]\n", cpu->cd.arm.ttb);
                        cpu->cd.arm.ttb &= 0xffffc000;
                }
                break;

        case 3: /*  Domain Access Control Register:  */
                if (l_bit)
                        cpu->cd.arm.r[rd] = cpu->cd.arm.dacr;
                else
                        cpu->cd.arm.dacr = cpu->cd.arm.r[rd];
                break;

        case 5: /*  Fault Status Register:  */
                /*  Note: Only the lowest 8 bits are defined.  */
                if (l_bit)
                        cpu->cd.arm.r[rd] = cpu->cd.arm.fsr & 0xff;
                else
                        cpu->cd.arm.fsr = cpu->cd.arm.r[rd] & 0xff;
                break;

        case 6: /*  Fault Address Register:  */
                if (l_bit)
                        cpu->cd.arm.r[rd] = cpu->cd.arm.far;
                else
                        cpu->cd.arm.far = cpu->cd.arm.r[rd];
                break;

        case 7: /*  Cache functions:  */
                if (l_bit) {
                        fatal("[ arm_coproc_15: attempt to read cr7? ]\n");
                        return;
                }
                /*  debug("[ arm_coproc_15: cache op: TODO ]\n");  */
                /*  TODO:  */
                break;

        case 8: /*  TLB functions:  */
                if (l_bit) {
                        fatal("[ arm_coproc_15: attempt to read cr8? ]\n");
                        return;
                }
                /*  fatal("[ arm_coproc_15: TLB: op2=%i crm=%i rd=0x%08x ]\n",
                    opcode2, crm, cpu->cd.arm.r[rd]);  */
                if (opcode2 == 0)
                        cpu->invalidate_translation_caches_paddr(cpu, 0,
                            INVALIDATE_ALL);
                else
                        cpu->invalidate_translation_caches_paddr(cpu,
                            cpu->cd.arm.r[rd], INVALIDATE_VADDR);
                break;

        case 13:/*  Process ID Register:  */
                if (opcode2 != 0)
                        fatal("[ arm_coproc_15: PID access, but opcode2 "
                            "= %i? (should be 0) ]\n", opcode2);
                if (crm != 0)
                        fatal("[ arm_coproc_15: PID access, but crm "
                            "= %i? (should be 0) ]\n", crm);
                if (l_bit)
                        cpu->cd.arm.r[rd] = cpu->cd.arm.pid;
                else
                        cpu->cd.arm.pid = cpu->cd.arm.r[rd];
                if (cpu->cd.arm.pid != 0) {
                        fatal("ARM TODO: pid!=0. Fast Context Switch"
                            " Extension not implemented yet\n");
                        exit(1);
                }
                break;

        case 15:/*  IMPLEMENTATION DEPENDANT!  */
                fatal("[ arm_coproc_15: TODO: IMPLEMENTATION DEPENDANT! ]\n");
                break;

        default:fatal("arm_coproc_15: unimplemented crn = %i\n", crn);
                fatal("(opcode1=%i opcode2=%i crm=%i rd=%i l=%i)\n",
                    opcode1, opcode2, crm, rd, l_bit);
                exit(1);
        }
}


/*****************************************************************************/


/*
 *  arm_coproc_i80321():
 *
 *  Intel 80321 coprocessor.
 */
void arm_coproc_i80321(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
        int crn, int crm, int rd)
{
        switch (crm) {
        case 0: fatal("[ 80321: crm 0: TODO ]\n");
                break;
        case 1: fatal("[ 80321: crm 1: TODO ]\n");
                switch (crn) {
                case 0: /*  tmr0:  */
                        break;
                case 2: /*  tcr0:  */
                        break;
                case 4: /*  trr0:  */
                        break;
                case 6: /*  tisr:  */
                        break;
                default:fatal("arm_coproc_i80321: unimplemented crn = %i\n",
                            crn);
                        fatal("(opcode1=%i opcode2=%i crm=%i rd=%i l=%i)\n",
                            opcode1, opcode2, crm, rd, l_bit);
                        exit(1);
                }
                break;
        default:fatal("arm_coproc_i80321: unimplemented opcode1=%i opcode2=%i"
                    " crn=%i crm=%i rd=%i l=%i)\n", opcode1, opcode2,
                    crn, crm, rd, l_bit);
                exit(1);
        }
}


/*
 *  arm_coproc_i80321_14():
 *
 *  Intel 80321 coprocessor 14.
 */
void arm_coproc_i80321_14(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
        int crn, int crm, int rd)
{
        switch (crm) {
        case 0: fatal("[ 80321_14: crm 0: TODO ]\n");
                break;
        default:fatal("arm_coproc_i80321_14: unimplemented opcode1=%i opcode2="
                    "%i crn=%i crm=%i rd=%i l=%i)\n", opcode1, opcode2,
                    crn, crm, rd, l_bit);
                exit(1);
        }
}

1	/*
2	* Copyright (C) 2005 Anders Gavare. All rights reserved.
3	*
4	* Redistribution and use in source and binary forms, with or without
5	* modification, are permitted provided that the following conditions are met:
6	*
7	* 1. Redistributions of source code must retain the above copyright
8	* notice, this list of conditions and the following disclaimer.
9	* 2. Redistributions in binary form must reproduce the above copyright
10	* notice, this list of conditions and the following disclaimer in the
11	* documentation and/or other materials provided with the distribution.
12	* 3. The name of the author may not be used to endorse or promote products
13	* derived from this software without specific prior written permission.
14	*
15	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25	* SUCH DAMAGE.
26	*
27	*
28	* $Id: cpu_arm_coproc.c,v 1.10 2005/10/07 22:10:51 debug Exp $
29	*
30	* ARM coprocessor emulation.
31	*/
32
33	#include <stdio.h>
34	#include <stdlib.h>
35	#include <string.h>
36	#include <ctype.h>
37
38	#include "cpu.h"
39	#include "misc.h"
40	#include "symbol.h"
41
42
43	/*
44	* arm_coproc_15():
45	*
46	* The system control coprocessor.
47	*/
48	void arm_coproc_15(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
49	int crn, int crm, int rd)
50	{
51	uint32_t old_control;
52
53	/* Some sanity checks: */
54	if (opcode1 != 0) {
55	fatal("arm_coproc_15: opcode1 = %i, should be 0\n", opcode1);
56	exit(1);
57	}
58	if (rd == ARM_PC) {
59	fatal("arm_coproc_15: rd = PC\n");
60	exit(1);
61	}
62
63	switch (crn) {
64
65	case 0: /* Main ID register: */
66	if (opcode2 != 0)
67	fatal("[ arm_coproc_15: TODO: cr0, opcode2=%i ]\n",
68	opcode2);
69	if (l_bit)
70	cpu->cd.arm.r[rd] = cpu->cd.arm.cpu_type.cpu_id;
71	else
72	fatal("[ arm_coproc_15: attempt to write to cr0? ]\n");
73	break;
74
75	case 1: /* Control Register: */
76	if (l_bit) {
77	cpu->cd.arm.r[rd] = cpu->cd.arm.control;
78	return;
79	}
80	/*
81	* Write to control: Check each bit individually:
82	*/
83	old_control = cpu->cd.arm.control;
84	cpu->cd.arm.control = cpu->cd.arm.r[rd];
85	if ((old_control & ARM_CONTROL_MMU) !=
86	(cpu->cd.arm.control & ARM_CONTROL_MMU))
87	debug("[ %s the MMU ]\n", cpu->cd.arm.control &
88	ARM_CONTROL_MMU? "enabling" : "disabling");
89	if ((old_control & ARM_CONTROL_ALIGN) !=
90	(cpu->cd.arm.control & ARM_CONTROL_ALIGN))
91	debug("[ %s alignment checks ]\n", cpu->cd.arm.control &
92	ARM_CONTROL_ALIGN? "enabling" : "disabling");
93	if ((old_control & ARM_CONTROL_CACHE) !=
94	(cpu->cd.arm.control & ARM_CONTROL_CACHE))
95	debug("[ %s the [data] cache ]\n", cpu->cd.arm.control &
96	ARM_CONTROL_CACHE? "enabling" : "disabling");
97	if ((old_control & ARM_CONTROL_WBUFFER) !=
98	(cpu->cd.arm.control & ARM_CONTROL_WBUFFER))
99	debug("[ %s the write buffer ]\n", cpu->cd.arm.control &
100	ARM_CONTROL_WBUFFER? "enabling" : "disabling");
101	if ((old_control & ARM_CONTROL_BIG) !=
102	(cpu->cd.arm.control & ARM_CONTROL_BIG)) {
103	fatal("ERROR: Trying to switch endianness. Not "
104	"supported yet.\n");
105	exit(1);
106	}
107	if ((old_control & ARM_CONTROL_ICACHE) !=
108	(cpu->cd.arm.control & ARM_CONTROL_ICACHE))
109	debug("[ %s the icache ]\n", cpu->cd.arm.control &
110	ARM_CONTROL_ICACHE? "enabling" : "disabling");
111	/* TODO: More bits. */
112	break;
113
114	case 2: /* Translation Table Base register: */
115	/* NOTE: 16 KB aligned. */
116	if (l_bit)
117	cpu->cd.arm.r[rd] = cpu->cd.arm.ttb & 0xffffc000;
118	else {
119	cpu->cd.arm.ttb = cpu->cd.arm.r[rd];
120	if (cpu->cd.arm.ttb & 0x3fff)
121	fatal("[ WARNING! low bits of new TTB non-"
122	"zero? 0x%08x ]\n", cpu->cd.arm.ttb);
123	cpu->cd.arm.ttb &= 0xffffc000;
124	}
125	break;
126
127	case 3: /* Domain Access Control Register: */
128	if (l_bit)
129	cpu->cd.arm.r[rd] = cpu->cd.arm.dacr;
130	else
131	cpu->cd.arm.dacr = cpu->cd.arm.r[rd];
132	break;
133
134	case 5: /* Fault Status Register: */
135	/* Note: Only the lowest 8 bits are defined. */
136	if (l_bit)
137	cpu->cd.arm.r[rd] = cpu->cd.arm.fsr & 0xff;
138	else
139	cpu->cd.arm.fsr = cpu->cd.arm.r[rd] & 0xff;
140	break;
141
142	case 6: /* Fault Address Register: */
143	if (l_bit)
144	cpu->cd.arm.r[rd] = cpu->cd.arm.far;
145	else
146	cpu->cd.arm.far = cpu->cd.arm.r[rd];
147	break;
148
149	case 7: /* Cache functions: */
150	if (l_bit) {
151	fatal("[ arm_coproc_15: attempt to read cr7? ]\n");
152	return;
153	}
154	/* debug("[ arm_coproc_15: cache op: TODO ]\n"); */
155	/* TODO: */
156	break;
157
158	case 8: /* TLB functions: */
159	if (l_bit) {
160	fatal("[ arm_coproc_15: attempt to read cr8? ]\n");
161	return;
162	}
163	/* fatal("[ arm_coproc_15: TLB: op2=%i crm=%i rd=0x%08x ]\n",
164	opcode2, crm, cpu->cd.arm.r[rd]); */
165	if (opcode2 == 0)
166	cpu->invalidate_translation_caches_paddr(cpu, 0,
167	INVALIDATE_ALL);
168	else
169	cpu->invalidate_translation_caches_paddr(cpu,
170	cpu->cd.arm.r[rd], INVALIDATE_VADDR);
171	break;
172
173	case 13:/* Process ID Register: */
174	if (opcode2 != 0)
175	fatal("[ arm_coproc_15: PID access, but opcode2 "
176	"= %i? (should be 0) ]\n", opcode2);
177	if (crm != 0)
178	fatal("[ arm_coproc_15: PID access, but crm "
179	"= %i? (should be 0) ]\n", crm);
180	if (l_bit)
181	cpu->cd.arm.r[rd] = cpu->cd.arm.pid;
182	else
183	cpu->cd.arm.pid = cpu->cd.arm.r[rd];
184	if (cpu->cd.arm.pid != 0) {
185	fatal("ARM TODO: pid!=0. Fast Context Switch"
186	" Extension not implemented yet\n");
187	exit(1);
188	}
189	break;
190
191	case 15:/* IMPLEMENTATION DEPENDANT! */
192	fatal("[ arm_coproc_15: TODO: IMPLEMENTATION DEPENDANT! ]\n");
193	break;
194
195	default:fatal("arm_coproc_15: unimplemented crn = %i\n", crn);
196	fatal("(opcode1=%i opcode2=%i crm=%i rd=%i l=%i)\n",
197	opcode1, opcode2, crm, rd, l_bit);
198	exit(1);
199	}
200	}
201
202
203	/*****************************************************************************/
204
205
206	/*
207	* arm_coproc_i80321():
208	*
209	* Intel 80321 coprocessor.
210	*/
211	void arm_coproc_i80321(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
212	int crn, int crm, int rd)
213	{
214	switch (crm) {
215	case 0: fatal("[ 80321: crm 0: TODO ]\n");
216	break;
217	case 1: fatal("[ 80321: crm 1: TODO ]\n");
218	switch (crn) {
219	case 0: /* tmr0: */
220	break;
221	case 2: /* tcr0: */
222	break;
223	case 4: /* trr0: */
224	break;
225	case 6: /* tisr: */
226	break;
227	default:fatal("arm_coproc_i80321: unimplemented crn = %i\n",
228	crn);
229	fatal("(opcode1=%i opcode2=%i crm=%i rd=%i l=%i)\n",
230	opcode1, opcode2, crm, rd, l_bit);
231	exit(1);
232	}
233	break;
234	default:fatal("arm_coproc_i80321: unimplemented opcode1=%i opcode2=%i"
235	" crn=%i crm=%i rd=%i l=%i)\n", opcode1, opcode2,
236	crn, crm, rd, l_bit);
237	exit(1);
238	}
239	}
240
241
242	/*
243	* arm_coproc_i80321_14():
244	*
245	* Intel 80321 coprocessor 14.
246	*/
247	void arm_coproc_i80321_14(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
248	int crn, int crm, int rd)
249	{
250	switch (crm) {
251	case 0: fatal("[ 80321_14: crm 0: TODO ]\n");
252	break;
253	default:fatal("arm_coproc_i80321_14: unimplemented opcode1=%i opcode2="
254	"%i crn=%i crm=%i rd=%i l=%i)\n", opcode1, opcode2,
255	crn, crm, rd, l_bit);
256	exit(1);
257	}
258	}
259