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dpavlin |
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/* |
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* Copyright (C) 2005 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: cpu_arm_instr_loadstore.c,v 1.7 2005/08/16 05:37:10 debug Exp $ |
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* |
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* |
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* TODO: Native load/store if the endianness is the same as the host's |
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* (and check for alignment?) |
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*/ |
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#ifdef A__REG |
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void A__NAME__general(struct cpu *cpu, struct arm_instr_call *ic) { } |
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void A__NAME(struct cpu *cpu, struct arm_instr_call *ic) |
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{fatal("TODO: blah...\n");} |
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#else /* !A__REG */ |
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void A__NAME__general(struct cpu *cpu, struct arm_instr_call *ic) |
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{ |
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#ifdef A__B |
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unsigned char data[1]; |
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#else |
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unsigned char data[4]; |
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#endif |
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uint32_t addr; |
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addr = *((uint32_t *)ic->arg[0]) |
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#ifdef A__P |
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#ifdef A__U |
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+ |
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#else |
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- |
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#endif |
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#ifdef A__FIXINC |
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A__FIXINC; |
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#else |
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ic->arg[1]; |
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#endif |
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#endif |
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; |
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#ifdef A__L |
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if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data), |
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MEM_READ, CACHE_DATA)) { |
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fatal("load failed: TODO\n"); |
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exit(1); |
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} |
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#ifdef A__B |
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*((uint32_t *)ic->arg[2]) = data[0]; |
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#else |
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*((uint32_t *)ic->arg[2]) = data[0] + (data[1] << 8) + |
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(data[2] << 16) + (data[3] << 24); |
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#endif |
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#else |
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#ifdef A__B |
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data[0] = *((uint32_t *)ic->arg[2]); |
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#else |
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data[0] = (*((uint32_t *)ic->arg[2])); |
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data[1] = (*((uint32_t *)ic->arg[2])) >> 8; |
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data[2] = (*((uint32_t *)ic->arg[2])) >> 16; |
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data[3] = (*((uint32_t *)ic->arg[2])) >> 24; |
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#endif |
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if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data), |
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MEM_WRITE, CACHE_DATA)) { |
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fatal("store failed: TODO\n"); |
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exit(1); |
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} |
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#endif |
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#ifdef A__P |
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#ifdef A__W |
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*((uint32_t *)ic->arg[0]) = addr; |
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#endif |
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#else /* post-index writeback */ |
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*((uint32_t *)ic->arg[0]) = addr |
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#ifdef A__U |
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+ |
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#else |
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- |
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#endif |
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#ifdef A__FIXINC |
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A__FIXINC; |
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#else |
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ic->arg[1]; |
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#endif |
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#endif |
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} |
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void A__NAME(struct cpu *cpu, struct arm_instr_call *ic) |
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{ |
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uint32_t addr = *((uint32_t *)ic->arg[0]) |
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#ifdef A__P |
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#ifdef A__U |
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+ |
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#else |
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- |
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#endif |
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#ifdef A__FIXINC |
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A__FIXINC |
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#else |
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ic->arg[1] |
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#endif |
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#endif |
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; |
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unsigned char *page = cpu->cd.arm. |
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#ifdef A__L |
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host_load |
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#else |
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host_store |
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#endif |
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[addr >> 12]; |
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if (page == NULL) { |
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A__NAME__general(cpu, ic); |
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} else { |
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#ifdef A__P |
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#ifdef A__W |
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*((uint32_t *)ic->arg[0]) = addr; |
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#endif |
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#else /* post-index writeback */ |
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*((uint32_t *)ic->arg[0]) = addr |
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#ifdef A__U |
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+ |
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#else |
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- |
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#endif |
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#ifdef A__FIXINC |
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A__FIXINC; |
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#else |
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ic->arg[1]; |
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#endif |
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#endif |
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#ifdef A__L |
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#ifdef A__B |
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*((uint32_t *)ic->arg[2]) = page[addr & 4095]; |
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#else |
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addr &= 4095; |
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*((uint32_t *)ic->arg[2]) = page[addr] + |
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(page[addr + 1] << 8) + |
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(page[addr + 2] << 16) + |
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(page[addr + 3] << 24); |
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#endif |
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#else |
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#ifdef A__B |
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page[addr & 4095] = *((uint32_t *)ic->arg[2]); |
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#else |
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addr &= 4095; |
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page[addr] = *((uint32_t *)ic->arg[2]); |
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page[addr+1] = (*((uint32_t *)ic->arg[2])) >> 8; |
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page[addr+2] = (*((uint32_t *)ic->arg[2])) >> 16; |
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page[addr+3] = (*((uint32_t *)ic->arg[2])) >> 24; |
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#endif |
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#endif |
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} |
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} |
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#endif |
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#ifndef A__NOCONDITIONS |
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void A__NAME__eq(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (cpu->cd.arm.flags & ARM_FLAG_Z) A__NAME(cpu, ic); } |
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void A__NAME__ne(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (!(cpu->cd.arm.flags & ARM_FLAG_Z)) A__NAME(cpu, ic); } |
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void A__NAME__cs(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (cpu->cd.arm.flags & ARM_FLAG_C) A__NAME(cpu, ic); } |
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void A__NAME__cc(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (!(cpu->cd.arm.flags & ARM_FLAG_C)) A__NAME(cpu, ic); } |
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void A__NAME__mi(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (cpu->cd.arm.flags & ARM_FLAG_N) A__NAME(cpu, ic); } |
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void A__NAME__pl(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (!(cpu->cd.arm.flags & ARM_FLAG_N)) A__NAME(cpu, ic); } |
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void A__NAME__vs(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (cpu->cd.arm.flags & ARM_FLAG_V) A__NAME(cpu, ic); } |
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void A__NAME__vc(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (!(cpu->cd.arm.flags & ARM_FLAG_V)) A__NAME(cpu, ic); } |
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void A__NAME__hi(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (cpu->cd.arm.flags & ARM_FLAG_C && |
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!(cpu->cd.arm.flags & ARM_FLAG_Z)) A__NAME(cpu, ic); } |
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void A__NAME__ls(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (cpu->cd.arm.flags & ARM_FLAG_Z && |
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!(cpu->cd.arm.flags & ARM_FLAG_C)) A__NAME(cpu, ic); } |
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void A__NAME__ge(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (((cpu->cd.arm.flags & ARM_FLAG_N)?1:0) == |
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((cpu->cd.arm.flags & ARM_FLAG_V)?1:0)) A__NAME(cpu, ic); } |
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void A__NAME__lt(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (((cpu->cd.arm.flags & ARM_FLAG_N)?1:0) != |
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((cpu->cd.arm.flags & ARM_FLAG_V)?1:0)) A__NAME(cpu, ic); } |
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void A__NAME__gt(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (((cpu->cd.arm.flags & ARM_FLAG_N)?1:0) == |
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((cpu->cd.arm.flags & ARM_FLAG_V)?1:0) && |
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!(cpu->cd.arm.flags & ARM_FLAG_Z)) A__NAME(cpu, ic); } |
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void A__NAME__le(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (((cpu->cd.arm.flags & ARM_FLAG_N)?1:0) != |
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((cpu->cd.arm.flags & ARM_FLAG_V)?1:0) || |
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(cpu->cd.arm.flags & ARM_FLAG_Z)) A__NAME(cpu, ic); } |
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#endif |
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