25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: interrupts.c,v 1.9 2006/05/17 20:27:31 debug Exp $ |
* $Id: interrupts.c,v 1.10 2006/08/14 17:45:47 debug Exp $ |
29 |
* |
* |
30 |
* Machine-dependent interrupt glue. |
* Machine-dependent interrupt glue. |
31 |
*/ |
*/ |
707 |
/* |
/* |
708 |
* Interrupt function for Cobalt, evbmips (Malta), and Algor. |
* Interrupt function for Cobalt, evbmips (Malta), and Algor. |
709 |
* |
* |
710 |
|
* Most machines will not use secondary_mask1 and native_secondary_irq. |
711 |
|
* Algor, however, routes COM1 and COM2 interrupts to MIPS CPU interrupt 4 |
712 |
|
* (called "secondary" here), and IDE interrupts to CPU interrupt 2. |
713 |
|
* |
714 |
* (irq_nr = 8 + 16 can be used to just reassert/deassert interrupts.) |
* (irq_nr = 8 + 16 can be used to just reassert/deassert interrupts.) |
715 |
*/ |
*/ |
716 |
void isa8_interrupt(struct machine *m, struct cpu *cpu, int irq_nr, int assrt) |
void isa8_interrupt(struct machine *m, struct cpu *cpu, int irq_nr, int assrt) |
758 |
m->isa_pic_data.last_int = x; |
m->isa_pic_data.last_int = x; |
759 |
} |
} |
760 |
|
|
761 |
if (m->isa_pic_data.pic1->irr & ~m->isa_pic_data.pic1->ier) |
if (m->isa_pic_data.secondary_mask1 & |
762 |
|
m->isa_pic_data.pic1->irr & ~m->isa_pic_data.pic1->ier) |
763 |
|
cpu_interrupt(cpu, m->isa_pic_data.native_secondary_irq); |
764 |
|
else |
765 |
|
cpu_interrupt_ack(cpu, m->isa_pic_data.native_secondary_irq); |
766 |
|
|
767 |
|
if (~m->isa_pic_data.secondary_mask1 & |
768 |
|
m->isa_pic_data.pic1->irr & ~m->isa_pic_data.pic1->ier) |
769 |
cpu_interrupt(cpu, m->isa_pic_data.native_irq); |
cpu_interrupt(cpu, m->isa_pic_data.native_irq); |
770 |
else |
else |
771 |
cpu_interrupt_ack(cpu, m->isa_pic_data.native_irq); |
cpu_interrupt_ack(cpu, m->isa_pic_data.native_irq); |