--- trunk/src/include/cpu_arm.h	2007/10/08 16:18:22	9
+++ trunk/src/include/cpu_arm.h	2007/10/08 16:18:27	10
@@ -28,7 +28,7 @@
  *  SUCH DAMAGE.
  *
  *
- *  $Id: cpu_arm.h,v 1.1 2005/06/03 07:39:28 debug Exp $
+ *  $Id: cpu_arm.h,v 1.10 2005/06/26 22:23:43 debug Exp $
  */
 
 #include "misc.h"
@@ -36,8 +36,96 @@
 
 struct cpu_family;
 
+#define	ARM_SL			10
+#define	ARM_FP			11
+#define	ARM_IP			12
+#define	ARM_SP			13
+#define	ARM_LR			14
+#define	ARM_PC			15
+#define	N_ARM_REGS		16
+
+/*
+ *  Translated instruction calls:
+ *
+ *  The translation cache begins with N_BASE_TABLE_ENTRIES uint32_t offsets
+ *  to arm_tc_physpage structs.
+ */
+#define	N_IC_ARGS			3
+#define	IC_ENTRIES_SHIFT		10
+#define	IC_ENTRIES_PER_PAGE		(1 << IC_ENTRIES_SHIFT)
+#define	PC_TO_IC_ENTRY(a)		(((a) >> 2) & (IC_ENTRIES_PER_PAGE-1))
+#define	ADDR_TO_PAGENR(a)		((a) >> (IC_ENTRIES_SHIFT+2))
+#define	N_BASE_TABLE_ENTRIES		32768
+#define	PAGENR_TO_TABLE_INDEX(a)	((a) & (N_BASE_TABLE_ENTRIES-1))
+#define	ARM_TRANSLATION_CACHE_SIZE	(1048576 * 16)
+#define	ARM_TRANSLATION_CACHE_MARGIN	65536
+
+struct arm_instr_call {
+	void	(*f)(struct cpu *, struct arm_instr_call *);
+	size_t	arg[N_IC_ARGS];
+};
+
+struct arm_tc_physpage {
+	uint32_t	next_ofs;	/*  or 0 for end of chain  */
+	uint32_t	physaddr;
+	int		flags;
+	struct arm_instr_call ics[IC_ENTRIES_PER_PAGE + 1];
+};
+
+#define	ARM_COMBINATIONS		1
+
+#define	ARM_FLAG_N	0x80000000	/*  Negative flag  */
+#define	ARM_FLAG_Z	0x40000000	/*  Zero flag  */
+#define	ARM_FLAG_C	0x20000000	/*  Carry flag  */
+#define	ARM_FLAG_V	0x10000000	/*  Overflow flag  */
+#define	ARM_FLAG_I	0x00000080	/*  Interrupt disable  */
+#define	ARM_FLAG_F	0x00000040	/*  Fast Interrupt disable  */
+
+#define	ARM_FLAG_MODE	0x0000001f
+#define	ARM_MODE_USR26	      0x00
+#define	ARM_MODE_FIQ26	      0x01
+#define	ARM_MODE_IRQ26	      0x02
+#define	ARM_MODE_SVC26	      0x03
+#define	ARM_MODE_USR32	      0x10
+#define	ARM_MODE_FIQ32	      0x11
+#define	ARM_MODE_IRQ32	      0x12
+#define	ARM_MODE_SVC32	      0x13
+#define	ARM_MODE_ABT32	      0x17
+#define	ARM_MODE_UND32	      0x1b
+
 struct arm_cpu {
-	int		dummy;
+	uint32_t		flags;
+
+	/*
+	 *  General Purpose Registers (including the program counter):
+	 *
+	 *  r[] always contains the current register set. The others are
+	 *  only used to swap to/from when changing modes. (An exception is
+	 *  r[0..7], which are never swapped out, they are always present.)
+	 */
+	uint32_t		r[N_ARM_REGS];
+	uint32_t		usr_r8_r14[7];
+	uint32_t		fiq_r8_r14[7];
+	uint32_t		irq_r13_r14[2];
+	uint32_t		svc_r13_r14[2];
+	uint32_t		abt_r13_r14[2];
+	uint32_t		und_r13_r14[2];
+
+	/*
+	 *  Instruction translation cache:
+	 */
+	unsigned char		*translation_cache;
+	size_t			translation_cache_cur_ofs;
+
+	/*  cur_ic_page is a pointer to an array of IC_ENTRIES_PER_PAGE
+	    instruction call entries. next_ic points to the next such
+	    call to be executed.  */
+	struct arm_tc_physpage	*cur_physpage;
+	struct arm_instr_call	*cur_ic_page;
+	struct arm_instr_call	*next_ic;
+
+	int			running_translated;
+	int32_t			n_translated_instrs;
 };