50 |
#define CPC_PCI_IO_END 0xfbffffff |
#define CPC_PCI_IO_END 0xfbffffff |
51 |
|
|
52 |
/* PCI config space */ |
/* PCI config space */ |
53 |
#define CPC_PCICFGADR 0xfee00000 |
#define CPC_PCICFGADR 0xfec00000 |
54 |
#define CPC_PCI_CONFIG_ENABLE 0x80000000 |
#define CPC_PCI_CONFIG_ENABLE 0x80000000 |
55 |
#define CPC_PCICFGDATA 0xfee00004 |
#define CPC_PCICFGDATA 0xfec00004 |
56 |
|
|
57 |
/* Config space regs */ |
/* Config space regs */ |
58 |
#define CPC_PCI_BRDGERR 0x48 |
#define CPC_PCI_BRDGERR 0x48 |
87 |
#define CPC_PTM2_MEMSIZE 0xff40003c |
#define CPC_PTM2_MEMSIZE 0xff40003c |
88 |
|
|
89 |
/* serial ports */ |
/* serial ports */ |
90 |
#define CPC_COM0 0xfc004500ULL |
#define CPC_COM0 0xff600300ULL |
91 |
#define CPC_COM1 0xfc004600ULL |
#define CPC_COM1 0xff600400ULL |
92 |
#define CPC_COM_SPEED(bus) ((bus) / (2 * 4)) |
#define CPC_COM_SPEED(bus) ((bus) / (2 * 4)) |
93 |
|
|
94 |
/* processor interface registers */ |
/* processor interface registers */ |
159 |
|
|
160 |
|
|
161 |
/* IIC */ |
/* IIC */ |
162 |
#define CPC_IIC0 0xfc020000 |
#define CPC_IIC0 0xff620000 |
163 |
#define CPC_IIC1 0xfc030000 |
#define CPC_IIC1 0xff630000 |
164 |
#define CPC_IIC_SIZE 0x00000014 |
#define CPC_IIC_SIZE 0x00000014 |
165 |
/* offsets from base */ |
/* offsets from base */ |
166 |
#define CPC_IIC_MDBUF 0x00000000 |
#define CPC_IIC_MDBUF 0x00000000 |
180 |
#define CPC_IIC_DIRECTCNTL 0x00000010 |
#define CPC_IIC_DIRECTCNTL 0x00000010 |
181 |
|
|
182 |
/* timer */ |
/* timer */ |
183 |
#define CPC_TIMER 0xfc050000 |
#define CPC_TIMER 0xff650000 |
184 |
#define CPC_GPTTBC 0x00000000 |
#define CPC_GPTTBC 0x00000000 |
185 |
|
|
186 |
#endif /* CPC700REG_H */ |
#endif /* CPC700REG_H */ |