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/* |
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* Copyright (C) 2004-2007 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: dev_wdc.c,v 1.76 2007/06/15 19:57:34 debug Exp $ |
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* |
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* COMMENT: Standard "wdc" IDE controller |
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*/ |
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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#include "cpu.h" |
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#include "device.h" |
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#include "diskimage.h" |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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#include "wdcreg.h" |
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#define DEV_WDC_LENGTH 8 |
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#define WDC_TICK_SHIFT 14 |
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#define WDC_MAX_SECTORS 512 |
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#define WDC_INBUF_SIZE (512*(WDC_MAX_SECTORS+1)) |
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extern int quiet_mode; |
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/* #define debug fatal */ |
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struct wdc_data { |
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struct interrupt irq; |
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int addr_mult; |
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int base_drive; |
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int data_debug; |
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int io_enabled; |
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|
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/* Cached values: */ |
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int cyls[2]; |
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int heads[2]; |
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int sectors_per_track[2]; |
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unsigned char *inbuf; |
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int inbuf_head; |
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int inbuf_tail; |
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int int_assert; |
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int write_in_progress; |
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int write_count; |
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int64_t write_offset; |
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int error; |
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int precomp; |
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int seccnt; |
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int sector; |
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int cyl_lo; |
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int cyl_hi; |
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int sectorsize; |
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int lba; |
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int drive; |
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int head; |
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int cur_command; |
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int atapi_cmd_in_progress; |
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int atapi_phase; |
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struct scsi_transfer *atapi_st; |
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int atapi_len; |
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size_t atapi_received; |
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unsigned char identify_struct[512]; |
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}; |
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#define COMMAND_RESET 0x100 |
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DEVICE_TICK(wdc) |
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{ |
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struct wdc_data *d = extra; |
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if (d->int_assert) |
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INTERRUPT_ASSERT(d->irq); |
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} |
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/* |
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* wdc_set_io_enabled(): |
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* |
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* Set io_enabled to zero to disable the I/O registers temporarily (e.g. |
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* used by PCI code in NetBSD to detect whether multiple controllers collide |
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* in I/O space). |
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* |
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* Return value is old contents of the io_enabled variable. |
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*/ |
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int wdc_set_io_enabled(struct wdc_data *d, int io_enabled) |
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{ |
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int old = d->io_enabled; |
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d->io_enabled = io_enabled; |
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return old; |
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} |
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/* |
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* wdc_addtoinbuf(): |
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* |
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* Write to the inbuf at its head, read at its tail. |
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*/ |
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static void wdc_addtoinbuf(struct wdc_data *d, int c) |
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{ |
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d->inbuf[d->inbuf_head] = c; |
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d->inbuf_head = (d->inbuf_head + 1) % WDC_INBUF_SIZE; |
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if (d->inbuf_head == d->inbuf_tail) |
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fatal("[ wdc_addtoinbuf(): WARNING! wdc inbuf overrun!" |
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" Increase WDC_MAX_SECTORS. ]\n"); |
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} |
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/* |
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* wdc_get_inbuf(): |
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* |
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* Read from the tail of inbuf. |
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*/ |
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static uint64_t wdc_get_inbuf(struct wdc_data *d) |
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{ |
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int c = d->inbuf[d->inbuf_tail]; |
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if (d->inbuf_head == d->inbuf_tail) { |
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fatal("[ wdc: WARNING! someone is reading too much from the " |
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"wdc inbuf! ]\n"); |
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return -1; |
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} |
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d->inbuf_tail = (d->inbuf_tail + 1) % WDC_INBUF_SIZE; |
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return c; |
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} |
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/* |
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* wdc_initialize_identify_struct(): |
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*/ |
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static void wdc_initialize_identify_struct(struct cpu *cpu, struct wdc_data *d) |
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{ |
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uint64_t total_size; |
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int flags, cdrom = 0; |
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char namebuf[40]; |
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total_size = diskimage_getsize(cpu->machine, d->drive + d->base_drive, |
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DISKIMAGE_IDE); |
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if (diskimage_is_a_cdrom(cpu->machine, d->drive + d->base_drive, |
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DISKIMAGE_IDE)) |
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cdrom = 1; |
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memset(d->identify_struct, 0, sizeof(d->identify_struct)); |
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/* Offsets are in 16-bit WORDS! High byte, then low. */ |
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/* 0: general flags */ |
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flags = 1 << 6; /* Fixed */ |
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if (cdrom) |
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flags = 0x8580; /* ATAPI, CDROM, removable */ |
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d->identify_struct[2 * 0 + 0] = flags >> 8; |
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d->identify_struct[2 * 0 + 1] = flags; |
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/* 1: nr of cylinders */ |
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d->identify_struct[2 * 1 + 0] = d->cyls[d->drive] >> 8; |
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d->identify_struct[2 * 1 + 1] = d->cyls[d->drive]; |
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/* 3: nr of heads */ |
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d->identify_struct[2 * 3 + 0] = d->heads[d->drive] >> 8; |
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d->identify_struct[2 * 3 + 1] = d->heads[d->drive]; |
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/* 6: sectors per track */ |
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d->identify_struct[2 * 6 + 0] = d->sectors_per_track[d->drive] >> 8; |
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d->identify_struct[2 * 6 + 1] = d->sectors_per_track[d->drive]; |
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/* 10-19: Serial number */ |
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memcpy(&d->identify_struct[2 * 10], "#0 ", 20); |
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/* 23-26: Firmware version */ |
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memcpy(&d->identify_struct[2 * 23], "1.0 ", 8); |
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/* 27-46: Model number */ |
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if (diskimage_getname(cpu->machine, d->drive + d->base_drive, |
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DISKIMAGE_IDE, namebuf, sizeof(namebuf))) { |
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size_t i; |
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for (i=0; i<sizeof(namebuf); i++) |
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if (namebuf[i] == 0) { |
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for (; i<sizeof(namebuf); i++) |
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namebuf[i] = ' '; |
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break; |
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} |
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memcpy(&d->identify_struct[2 * 27], namebuf, 40); |
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} else |
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memcpy(&d->identify_struct[2 * 27], |
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"Fake GXemul IDE disk ", 40); |
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/* 47: max sectors per multitransfer */ |
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d->identify_struct[2 * 47 + 0] = 0x80; |
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d->identify_struct[2 * 47 + 1] = 128; |
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/* 49: capabilities: */ |
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/* (0x200 = LBA, 0x100 = DMA support.) */ |
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d->identify_struct[2 * 49 + 0] = 0; |
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d->identify_struct[2 * 49 + 1] = 0; |
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/* 51: PIO timing mode. */ |
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d->identify_struct[2 * 51 + 0] = 0x00; /* ? */ |
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d->identify_struct[2 * 51 + 1] = 0x00; |
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/* 53: 0x02 = fields 64-70 valid, 0x01 = fields 54-58 valid */ |
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d->identify_struct[2 * 53 + 0] = 0x00; |
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d->identify_struct[2 * 53 + 1] = 0x02; |
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/* 57-58: current capacity in sectors */ |
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d->identify_struct[2 * 57 + 0] = ((total_size / 512) >> 24) % 255; |
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d->identify_struct[2 * 57 + 1] = ((total_size / 512) >> 16) % 255; |
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d->identify_struct[2 * 58 + 0] = ((total_size / 512) >> 8) % 255; |
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d->identify_struct[2 * 58 + 1] = (total_size / 512) & 255; |
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/* 60-61: total nr of addressable sectors */ |
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d->identify_struct[2 * 60 + 0] = ((total_size / 512) >> 24) % 255; |
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d->identify_struct[2 * 60 + 1] = ((total_size / 512) >> 16) % 255; |
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d->identify_struct[2 * 61 + 0] = ((total_size / 512) >> 8) % 255; |
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d->identify_struct[2 * 61 + 1] = (total_size / 512) & 255; |
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/* 64: Advanced PIO mode support. 0x02 = mode4, 0x01 = mode3 */ |
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d->identify_struct[2 * 64 + 0] = 0x00; |
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d->identify_struct[2 * 64 + 1] = 0x03; |
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/* 67, 68: PIO timing */ |
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d->identify_struct[2 * 67 + 0] = 0; |
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d->identify_struct[2 * 67 + 1] = 120; |
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d->identify_struct[2 * 68 + 0] = 0; |
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d->identify_struct[2 * 68 + 1] = 120; |
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dpavlin |
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} |
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/* |
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* wdc__read(): |
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*/ |
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void wdc__read(struct cpu *cpu, struct wdc_data *d) |
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{ |
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dpavlin |
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#define MAX_SECTORS_PER_CHUNK 64 |
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const int max_sectors_per_chunk = MAX_SECTORS_PER_CHUNK; |
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unsigned char buf[512 * MAX_SECTORS_PER_CHUNK]; |
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dpavlin |
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int i, cyl = d->cyl_hi * 256+ d->cyl_lo; |
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int count = d->seccnt? d->seccnt : 256; |
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uint64_t offset = 512 * (d->sector - 1 |
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dpavlin |
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+ (int64_t)d->head * d->sectors_per_track[d->drive] + |
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(int64_t)d->heads[d->drive] * d->sectors_per_track[d->drive] * cyl); |
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dpavlin |
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#if 0 |
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/* LBA: */ |
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if (d->lba) |
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offset = 512 * (((d->head & 0xf) << 24) + (cyl << 8) |
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+ d->sector); |
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printf("WDC read from offset %lli\n", (long long)offset); |
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#endif |
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while (count > 0) { |
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dpavlin |
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int to_read = count > max_sectors_per_chunk? |
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max_sectors_per_chunk : count; |
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/* TODO: result code from the read? */ |
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if (d->inbuf_head + 512 * to_read <= WDC_INBUF_SIZE) { |
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diskimage_access(cpu->machine, d->drive + d->base_drive, |
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DISKIMAGE_IDE, 0, offset, |
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d->inbuf + d->inbuf_head, 512 * to_read); |
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d->inbuf_head += 512 * to_read; |
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if (d->inbuf_head == WDC_INBUF_SIZE) |
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d->inbuf_head = 0; |
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} else { |
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diskimage_access(cpu->machine, d->drive + d->base_drive, |
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DISKIMAGE_IDE, 0, offset, buf, 512 * to_read); |
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for (i=0; i<512 * to_read; i++) |
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wdc_addtoinbuf(d, buf[i]); |
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} |
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offset += 512 * to_read; |
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count -= to_read; |
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dpavlin |
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} |
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dpavlin |
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d->int_assert = 1; |
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dpavlin |
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} |
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/* |
315 |
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* wdc__write(): |
316 |
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*/ |
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void wdc__write(struct cpu *cpu, struct wdc_data *d) |
318 |
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{ |
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int cyl = d->cyl_hi * 256+ d->cyl_lo; |
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int count = d->seccnt? d->seccnt : 256; |
321 |
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uint64_t offset = 512 * (d->sector - 1 |
322 |
dpavlin |
32 |
+ (int64_t)d->head * d->sectors_per_track[d->drive] + |
323 |
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(int64_t)d->heads[d->drive] * d->sectors_per_track[d->drive] * cyl); |
324 |
dpavlin |
14 |
#if 0 |
325 |
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/* LBA: */ |
326 |
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if (d->lba) |
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offset = 512 * (((d->head & 0xf) << 24) + |
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(cyl << 8) + d->sector); |
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printf("WDC write to offset %lli\n", (long long)offset); |
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#endif |
331 |
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dpavlin |
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d->write_in_progress = d->cur_command; |
333 |
dpavlin |
14 |
d->write_count = count; |
334 |
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d->write_offset = offset; |
335 |
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336 |
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/* TODO: result code? */ |
337 |
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} |
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339 |
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340 |
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/* |
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dpavlin |
4 |
* status_byte(): |
342 |
dpavlin |
14 |
* |
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* Return a reasonable status byte corresponding to the controller's current |
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* state. |
345 |
dpavlin |
4 |
*/ |
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static int status_byte(struct wdc_data *d, struct cpu *cpu) |
347 |
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{ |
348 |
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int odata = 0; |
349 |
dpavlin |
6 |
if (diskimage_exist(cpu->machine, d->drive + d->base_drive, |
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DISKIMAGE_IDE)) |
351 |
dpavlin |
14 |
odata |= WDCS_DRDY | WDCS_DSC; |
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dpavlin |
4 |
if (d->inbuf_head != d->inbuf_tail) |
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odata |= WDCS_DRQ; |
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if (d->write_in_progress) |
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odata |= WDCS_DRQ; |
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if (d->error) |
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|
|
odata |= WDCS_ERR; |
358 |
dpavlin |
20 |
if (d->atapi_cmd_in_progress && (d->atapi_phase & WDCS_DRQ)) { |
359 |
|
|
odata |= WDCS_DRQ; |
360 |
|
|
} |
361 |
dpavlin |
4 |
return odata; |
362 |
|
|
} |
363 |
|
|
|
364 |
|
|
|
365 |
dpavlin |
22 |
DEVICE_ACCESS(wdc_altstatus) |
366 |
dpavlin |
4 |
{ |
367 |
|
|
struct wdc_data *d = extra; |
368 |
|
|
uint64_t idata = 0, odata = 0; |
369 |
|
|
|
370 |
dpavlin |
18 |
idata = data[0]; |
371 |
dpavlin |
4 |
|
372 |
dpavlin |
20 |
/* Same as the normal status byte: */ |
373 |
dpavlin |
4 |
odata = status_byte(d, cpu); |
374 |
|
|
|
375 |
|
|
if (writeflag==MEM_READ) |
376 |
|
|
debug("[ wdc: read from ALTSTATUS: 0x%02x ]\n", |
377 |
|
|
(int)odata); |
378 |
dpavlin |
20 |
else { |
379 |
dpavlin |
4 |
debug("[ wdc: write to ALT. CTRL: 0x%02x ]\n", |
380 |
|
|
(int)idata); |
381 |
dpavlin |
20 |
if (idata & WDCTL_4BIT) |
382 |
|
|
d->cur_command = COMMAND_RESET; |
383 |
|
|
} |
384 |
dpavlin |
4 |
|
385 |
|
|
if (writeflag == MEM_READ) |
386 |
dpavlin |
18 |
data[0] = odata; |
387 |
dpavlin |
4 |
|
388 |
|
|
return 1; |
389 |
|
|
} |
390 |
|
|
|
391 |
|
|
|
392 |
|
|
/* |
393 |
dpavlin |
20 |
* wdc_command(): |
394 |
|
|
*/ |
395 |
|
|
void wdc_command(struct cpu *cpu, struct wdc_data *d, int idata) |
396 |
|
|
{ |
397 |
dpavlin |
22 |
size_t i; |
398 |
dpavlin |
20 |
|
399 |
|
|
d->cur_command = idata; |
400 |
|
|
d->atapi_cmd_in_progress = 0; |
401 |
|
|
d->error = 0; |
402 |
|
|
|
403 |
|
|
/* |
404 |
|
|
* Disk images that do not exist return an ABORT error. This also |
405 |
|
|
* happens with CDROM images with the WDCC_IDENTIFY command; CDROM |
406 |
|
|
* images must be detected with ATAPI_IDENTIFY_DEVICE instead. |
407 |
|
|
* |
408 |
|
|
* TODO: Is this correct/good behaviour? |
409 |
|
|
*/ |
410 |
|
|
if (!diskimage_exist(cpu->machine, d->drive + d->base_drive, |
411 |
|
|
DISKIMAGE_IDE)) { |
412 |
|
|
debug("[ wdc: command 0x%02x drive %i, but no disk image ]\n", |
413 |
|
|
d->cur_command, d->drive + d->base_drive); |
414 |
|
|
d->error |= WDCE_ABRT; |
415 |
dpavlin |
34 |
d->int_assert = 1; |
416 |
dpavlin |
20 |
return; |
417 |
|
|
} |
418 |
|
|
if (diskimage_is_a_cdrom(cpu->machine, d->drive + d->base_drive, |
419 |
|
|
DISKIMAGE_IDE) && d->cur_command == WDCC_IDENTIFY) { |
420 |
|
|
debug("[ wdc: IDENTIFY drive %i, but it is an ATAPI " |
421 |
|
|
"drive ]\n", d->drive + d->base_drive); |
422 |
|
|
d->error |= WDCE_ABRT; |
423 |
dpavlin |
34 |
d->int_assert = 1; |
424 |
dpavlin |
20 |
return; |
425 |
|
|
} |
426 |
|
|
|
427 |
|
|
/* Handle the command: */ |
428 |
|
|
switch (d->cur_command) { |
429 |
|
|
|
430 |
|
|
case WDCC_READ: |
431 |
|
|
case WDCC_READMULTI: |
432 |
|
|
if (!quiet_mode) |
433 |
|
|
debug("[ wdc: READ from drive %i, head %i, cyl %i, " |
434 |
|
|
"sector %i, nsecs %i ]\n", d->drive, d->head, |
435 |
|
|
d->cyl_hi*256+d->cyl_lo, d->sector, d->seccnt); |
436 |
|
|
wdc__read(cpu, d); |
437 |
|
|
break; |
438 |
|
|
|
439 |
|
|
case WDCC_WRITE: |
440 |
|
|
case WDCC_WRITEMULTI: |
441 |
|
|
if (!quiet_mode) |
442 |
|
|
debug("[ wdc: WRITE to drive %i, head %i, cyl %i, " |
443 |
|
|
"sector %i, nsecs %i ]\n", d->drive, d->head, |
444 |
|
|
d->cyl_hi*256+d->cyl_lo, d->sector, d->seccnt); |
445 |
|
|
wdc__write(cpu, d); |
446 |
|
|
break; |
447 |
|
|
|
448 |
|
|
case WDCC_IDP: /* Initialize drive parameters */ |
449 |
|
|
debug("[ wdc: IDP drive %i (TODO) ]\n", d->drive); |
450 |
|
|
/* TODO */ |
451 |
dpavlin |
34 |
d->int_assert = 1; |
452 |
dpavlin |
20 |
break; |
453 |
|
|
|
454 |
|
|
case SET_FEATURES: |
455 |
|
|
debug("[ wdc: SET_FEATURES drive %i (TODO), feature 0x%02x ]\n", |
456 |
|
|
d->drive, d->precomp); |
457 |
|
|
/* TODO */ |
458 |
|
|
switch (d->precomp) { |
459 |
|
|
case WDSF_SET_MODE: |
460 |
|
|
debug("[ wdc: WDSF_SET_MODE drive %i, pio/dma flags " |
461 |
|
|
"0x%02x ]\n", d->drive, d->seccnt); |
462 |
|
|
break; |
463 |
|
|
default:d->error |= WDCE_ABRT; |
464 |
|
|
} |
465 |
|
|
/* TODO: always interrupt? */ |
466 |
dpavlin |
34 |
d->int_assert = 1; |
467 |
dpavlin |
20 |
break; |
468 |
|
|
|
469 |
|
|
case WDCC_RECAL: |
470 |
|
|
debug("[ wdc: RECAL drive %i ]\n", d->drive); |
471 |
dpavlin |
34 |
d->int_assert = 1; |
472 |
dpavlin |
20 |
break; |
473 |
|
|
|
474 |
|
|
case WDCC_IDENTIFY: |
475 |
|
|
case ATAPI_IDENTIFY_DEVICE: |
476 |
|
|
debug("[ wdc: %sIDENTIFY drive %i ]\n", d->cur_command == |
477 |
|
|
ATAPI_IDENTIFY_DEVICE? "ATAPI " : "", d->drive); |
478 |
|
|
wdc_initialize_identify_struct(cpu, d); |
479 |
|
|
/* The IDENTIFY data is sent out in low/high byte order: */ |
480 |
|
|
for (i=0; i<sizeof(d->identify_struct); i+=2) { |
481 |
|
|
wdc_addtoinbuf(d, d->identify_struct[i+1]); |
482 |
|
|
wdc_addtoinbuf(d, d->identify_struct[i+0]); |
483 |
|
|
} |
484 |
dpavlin |
34 |
d->int_assert = 1; |
485 |
dpavlin |
20 |
break; |
486 |
|
|
|
487 |
|
|
case WDCC_IDLE_IMMED: |
488 |
|
|
debug("[ wdc: IDLE_IMMED drive %i ]\n", d->drive); |
489 |
|
|
/* TODO: interrupt here? */ |
490 |
dpavlin |
34 |
d->int_assert = 1; |
491 |
dpavlin |
20 |
break; |
492 |
|
|
|
493 |
|
|
case WDCC_SETMULTI: |
494 |
|
|
debug("[ wdc: SETMULTI drive %i ]\n", d->drive); |
495 |
|
|
/* TODO: interrupt here? */ |
496 |
dpavlin |
34 |
d->int_assert = 1; |
497 |
dpavlin |
20 |
break; |
498 |
|
|
|
499 |
|
|
case ATAPI_SOFT_RESET: |
500 |
|
|
debug("[ wdc: ATAPI_SOFT_RESET drive %i ]\n", d->drive); |
501 |
|
|
/* TODO: interrupt here? */ |
502 |
dpavlin |
34 |
d->int_assert = 1; |
503 |
dpavlin |
20 |
break; |
504 |
|
|
|
505 |
|
|
case ATAPI_PKT_CMD: |
506 |
|
|
debug("[ wdc: ATAPI_PKT_CMD drive %i ]\n", d->drive); |
507 |
|
|
/* TODO: interrupt here? */ |
508 |
dpavlin |
34 |
/* d->int_assert = 1; */ |
509 |
dpavlin |
20 |
d->atapi_cmd_in_progress = 1; |
510 |
|
|
d->atapi_phase = PHASE_CMDOUT; |
511 |
|
|
break; |
512 |
|
|
|
513 |
dpavlin |
22 |
case WDCC_DIAGNOSE: |
514 |
|
|
debug("[ wdc: WDCC_DIAGNOSE drive %i: TODO ]\n", d->drive); |
515 |
|
|
/* TODO: interrupt here? */ |
516 |
dpavlin |
34 |
d->int_assert = 1; |
517 |
dpavlin |
22 |
d->error = 1; /* No error? */ |
518 |
|
|
break; |
519 |
|
|
|
520 |
dpavlin |
20 |
/* Unsupported commands, without warning: */ |
521 |
|
|
case WDCC_SEC_SET_PASSWORD: |
522 |
|
|
case WDCC_SEC_UNLOCK: |
523 |
|
|
case WDCC_SEC_ERASE_PREPARE: |
524 |
|
|
case WDCC_SEC_ERASE_UNIT: |
525 |
|
|
case WDCC_SEC_FREEZE_LOCK: |
526 |
|
|
case WDCC_SEC_DISABLE_PASSWORD: |
527 |
|
|
d->error |= WDCE_ABRT; |
528 |
|
|
break; |
529 |
|
|
|
530 |
|
|
default:/* TODO */ |
531 |
|
|
d->error |= WDCE_ABRT; |
532 |
|
|
fatal("[ wdc: WARNING! Unimplemented command 0x%02x (drive %i," |
533 |
|
|
" head %i, cyl %i, sector %i, nsecs %i) ]\n", |
534 |
|
|
d->cur_command, d->drive, d->head, d->cyl_hi*256+d->cyl_lo, |
535 |
|
|
d->sector, d->seccnt); |
536 |
|
|
} |
537 |
|
|
} |
538 |
|
|
|
539 |
|
|
|
540 |
dpavlin |
22 |
DEVICE_ACCESS(wdc) |
541 |
dpavlin |
4 |
{ |
542 |
|
|
struct wdc_data *d = extra; |
543 |
|
|
uint64_t idata = 0, odata = 0; |
544 |
dpavlin |
14 |
int i; |
545 |
dpavlin |
4 |
|
546 |
dpavlin |
22 |
relative_addr /= d->addr_mult; |
547 |
|
|
|
548 |
dpavlin |
30 |
if (!d->io_enabled) |
549 |
|
|
goto ret; |
550 |
|
|
|
551 |
dpavlin |
18 |
if (writeflag == MEM_WRITE) { |
552 |
|
|
if (relative_addr == wd_data) |
553 |
|
|
idata = memory_readmax64(cpu, data, len); |
554 |
dpavlin |
20 |
else { |
555 |
|
|
if (len != 1) |
556 |
|
|
fatal("[ wdc: WARNING! non-8-bit access! ]\n"); |
557 |
dpavlin |
18 |
idata = data[0]; |
558 |
dpavlin |
20 |
} |
559 |
dpavlin |
18 |
} |
560 |
dpavlin |
4 |
|
561 |
|
|
switch (relative_addr) { |
562 |
|
|
|
563 |
|
|
case wd_data: /* 0: data */ |
564 |
dpavlin |
18 |
if (writeflag == MEM_READ) { |
565 |
dpavlin |
22 |
odata = wdc_get_inbuf(d); |
566 |
dpavlin |
4 |
|
567 |
dpavlin |
20 |
if (cpu->byte_order == EMUL_LITTLE_ENDIAN) { |
568 |
|
|
if (len >= 2) |
569 |
|
|
odata += (wdc_get_inbuf(d) << 8); |
570 |
|
|
if (len == 4) { |
571 |
|
|
odata += (wdc_get_inbuf(d) << 16); |
572 |
|
|
odata += (wdc_get_inbuf(d) << 24); |
573 |
|
|
} |
574 |
|
|
} else { |
575 |
|
|
if (len >= 2) |
576 |
|
|
odata = (odata << 8) + wdc_get_inbuf(d); |
577 |
|
|
if (len == 4) { |
578 |
|
|
odata = (odata << 8) + wdc_get_inbuf(d); |
579 |
|
|
odata = (odata << 8) + wdc_get_inbuf(d); |
580 |
|
|
} |
581 |
dpavlin |
4 |
} |
582 |
|
|
|
583 |
dpavlin |
20 |
if (d->data_debug) { |
584 |
dpavlin |
24 |
char *s = "0x%04"PRIx64" ]\n"; |
585 |
dpavlin |
20 |
if (len == 1) |
586 |
dpavlin |
24 |
s = "0x%02"PRIx64" ]\n"; |
587 |
dpavlin |
20 |
if (len == 4) |
588 |
dpavlin |
24 |
s = "0x%08"PRIx64" ]\n"; |
589 |
dpavlin |
20 |
if (len == 8) |
590 |
dpavlin |
24 |
s = "0x%016"PRIx64" ]\n"; |
591 |
dpavlin |
20 |
debug("[ wdc: read from DATA: "); |
592 |
dpavlin |
24 |
debug(s, (uint64_t) odata); |
593 |
dpavlin |
20 |
} |
594 |
|
|
|
595 |
|
|
if (d->atapi_cmd_in_progress) { |
596 |
|
|
d->atapi_len -= len; |
597 |
|
|
d->atapi_received += len; |
598 |
|
|
if (d->atapi_len == 0) { |
599 |
|
|
if (d->atapi_received < d->atapi_st-> |
600 |
|
|
data_in_len) { |
601 |
|
|
d->atapi_phase = PHASE_DATAIN; |
602 |
|
|
d->atapi_len = d->atapi_st-> |
603 |
|
|
data_in_len - |
604 |
|
|
d->atapi_received; |
605 |
|
|
if (d->atapi_len > 32768) |
606 |
|
|
d->atapi_len = 0; |
607 |
|
|
} else |
608 |
|
|
d->atapi_phase = |
609 |
|
|
PHASE_COMPLETED; |
610 |
dpavlin |
34 |
d->int_assert = 1; |
611 |
dpavlin |
20 |
} |
612 |
|
|
} else { |
613 |
dpavlin |
18 |
#if 0 |
614 |
dpavlin |
20 |
if (d->inbuf_tail != d->inbuf_head) |
615 |
dpavlin |
18 |
#else |
616 |
dpavlin |
20 |
if (d->inbuf_tail != d->inbuf_head && |
617 |
|
|
((d->inbuf_tail - d->inbuf_head) % 512) |
618 |
|
|
== 0) |
619 |
dpavlin |
18 |
#endif |
620 |
dpavlin |
34 |
d->int_assert = 1; |
621 |
dpavlin |
20 |
} |
622 |
dpavlin |
4 |
} else { |
623 |
|
|
int inbuf_len; |
624 |
dpavlin |
20 |
if (d->data_debug) { |
625 |
dpavlin |
24 |
char *s = "0x%04"PRIx64" ]\n"; |
626 |
dpavlin |
20 |
if (len == 1) |
627 |
dpavlin |
24 |
s = "0x%02"PRIx64" ]\n"; |
628 |
dpavlin |
20 |
if (len == 4) |
629 |
dpavlin |
24 |
s = "0x%08"PRIx64" ]\n"; |
630 |
dpavlin |
20 |
if (len == 8) |
631 |
dpavlin |
24 |
s = "0x%016"PRIx64" ]\n"; |
632 |
dpavlin |
20 |
debug("[ wdc: write to DATA: "); |
633 |
dpavlin |
24 |
debug(s, (uint64_t) idata); |
634 |
dpavlin |
20 |
} |
635 |
|
|
if (!d->write_in_progress && |
636 |
|
|
!d->atapi_cmd_in_progress) { |
637 |
dpavlin |
4 |
fatal("[ wdc: write to DATA, but not " |
638 |
|
|
"expecting any? (len=%i): 0x%08lx ]\n", |
639 |
|
|
(int)len, (long)idata); |
640 |
|
|
} |
641 |
|
|
|
642 |
dpavlin |
20 |
if (cpu->byte_order == EMUL_LITTLE_ENDIAN) { |
643 |
|
|
switch (len) { |
644 |
|
|
case 4: wdc_addtoinbuf(d, idata & 0xff); |
645 |
|
|
wdc_addtoinbuf(d, (idata >> 8) & 0xff); |
646 |
|
|
wdc_addtoinbuf(d, (idata >> 16) & 0xff); |
647 |
|
|
wdc_addtoinbuf(d, (idata >> 24) & 0xff); |
648 |
|
|
break; |
649 |
|
|
case 2: wdc_addtoinbuf(d, idata & 0xff); |
650 |
|
|
wdc_addtoinbuf(d, (idata >> 8) & 0xff); |
651 |
|
|
break; |
652 |
|
|
case 1: wdc_addtoinbuf(d, idata); break; |
653 |
|
|
default:fatal("wdc: unimplemented write " |
654 |
|
|
"len %i\n", len); |
655 |
|
|
exit(1); |
656 |
|
|
} |
657 |
|
|
} else { |
658 |
|
|
switch (len) { |
659 |
|
|
case 4: wdc_addtoinbuf(d, (idata >> 24) & 0xff); |
660 |
|
|
wdc_addtoinbuf(d, (idata >> 16) & 0xff); |
661 |
|
|
wdc_addtoinbuf(d, (idata >> 8) & 0xff); |
662 |
|
|
wdc_addtoinbuf(d, idata & 0xff); |
663 |
|
|
break; |
664 |
|
|
case 2: wdc_addtoinbuf(d, (idata >> 8) & 0xff); |
665 |
|
|
wdc_addtoinbuf(d, idata & 0xff); |
666 |
|
|
break; |
667 |
|
|
case 1: wdc_addtoinbuf(d, idata); break; |
668 |
|
|
default:fatal("wdc: unimplemented write " |
669 |
|
|
"len %i\n", len); |
670 |
|
|
exit(1); |
671 |
|
|
} |
672 |
dpavlin |
4 |
} |
673 |
|
|
|
674 |
|
|
inbuf_len = d->inbuf_head - d->inbuf_tail; |
675 |
|
|
while (inbuf_len < 0) |
676 |
|
|
inbuf_len += WDC_INBUF_SIZE; |
677 |
|
|
|
678 |
dpavlin |
20 |
if (d->atapi_cmd_in_progress && inbuf_len == 12) { |
679 |
dpavlin |
42 |
unsigned char *scsi_cmd; |
680 |
dpavlin |
20 |
int x = 0, res; |
681 |
|
|
|
682 |
dpavlin |
42 |
CHECK_ALLOCATION(scsi_cmd = malloc(12)); |
683 |
|
|
|
684 |
dpavlin |
20 |
if (d->atapi_st != NULL) |
685 |
|
|
scsi_transfer_free(d->atapi_st); |
686 |
|
|
d->atapi_st = scsi_transfer_alloc(); |
687 |
|
|
|
688 |
|
|
debug("[ wdc: ATAPI command ]\n"); |
689 |
|
|
|
690 |
|
|
while (inbuf_len > 0) { |
691 |
|
|
scsi_cmd[x++] = wdc_get_inbuf(d); |
692 |
|
|
inbuf_len --; |
693 |
|
|
} |
694 |
|
|
|
695 |
|
|
d->atapi_st->cmd = scsi_cmd; |
696 |
|
|
d->atapi_st->cmd_len = 12; |
697 |
|
|
|
698 |
|
|
if (scsi_cmd[0] == SCSIBLOCKCMD_READ_CAPACITY |
699 |
|
|
|| scsi_cmd[0] == SCSICMD_READ_10 |
700 |
|
|
|| scsi_cmd[0] == SCSICMD_MODE_SENSE10) |
701 |
|
|
d->atapi_st->cmd_len = 10; |
702 |
|
|
|
703 |
|
|
res = diskimage_scsicommand(cpu, |
704 |
|
|
d->drive + d->base_drive, DISKIMAGE_IDE, |
705 |
|
|
d->atapi_st); |
706 |
|
|
|
707 |
|
|
if (res == 0) { |
708 |
|
|
fatal("WDC: ATAPI scsi error?\n"); |
709 |
|
|
exit(1); |
710 |
|
|
} |
711 |
|
|
|
712 |
|
|
d->atapi_len = 0; |
713 |
|
|
d->atapi_received = 0; |
714 |
|
|
|
715 |
|
|
if (res == 1) { |
716 |
|
|
if (d->atapi_st->data_in != NULL) { |
717 |
|
|
int i; |
718 |
|
|
d->atapi_phase = PHASE_DATAIN; |
719 |
|
|
d->atapi_len = d->atapi_st-> |
720 |
|
|
data_in_len; |
721 |
|
|
for (i=0; i<d->atapi_len; i++) |
722 |
|
|
wdc_addtoinbuf(d, |
723 |
|
|
d->atapi_st-> |
724 |
|
|
data_in[i]); |
725 |
|
|
if (d->atapi_len > 32768) |
726 |
|
|
d->atapi_len = 32768; |
727 |
|
|
} else { |
728 |
|
|
d->atapi_phase = |
729 |
|
|
PHASE_COMPLETED; |
730 |
|
|
} |
731 |
|
|
} else { |
732 |
|
|
fatal("wdc atapi Dataout? TODO\n"); |
733 |
|
|
d->atapi_phase = PHASE_DATAOUT; |
734 |
|
|
exit(1); |
735 |
|
|
} |
736 |
|
|
|
737 |
dpavlin |
34 |
d->int_assert = 1; |
738 |
dpavlin |
20 |
} |
739 |
|
|
|
740 |
|
|
if (( d->write_in_progress == WDCC_WRITEMULTI && |
741 |
|
|
inbuf_len % (512 * d->write_count) == 0) |
742 |
|
|
|| |
743 |
|
|
( d->write_in_progress == WDCC_WRITE && |
744 |
|
|
inbuf_len % 512 == 0) ) { |
745 |
|
|
int count = (d->write_in_progress == |
746 |
|
|
WDCC_WRITEMULTI)? d->write_count : 1; |
747 |
dpavlin |
42 |
unsigned char *buf, *b; |
748 |
dpavlin |
18 |
|
749 |
dpavlin |
42 |
CHECK_ALLOCATION(buf = malloc(512 * count)); |
750 |
|
|
b = buf; |
751 |
dpavlin |
24 |
|
752 |
dpavlin |
18 |
if (d->inbuf_tail+512*count <= WDC_INBUF_SIZE) { |
753 |
|
|
b = d->inbuf + d->inbuf_tail; |
754 |
|
|
d->inbuf_tail = (d->inbuf_tail + 512 |
755 |
|
|
* count) % WDC_INBUF_SIZE; |
756 |
|
|
} else { |
757 |
|
|
for (i=0; i<512 * count; i++) |
758 |
|
|
buf[i] = wdc_get_inbuf(d); |
759 |
dpavlin |
4 |
} |
760 |
|
|
|
761 |
|
|
diskimage_access(cpu->machine, |
762 |
dpavlin |
6 |
d->drive + d->base_drive, DISKIMAGE_IDE, 1, |
763 |
dpavlin |
18 |
d->write_offset, b, 512 * count); |
764 |
dpavlin |
4 |
|
765 |
dpavlin |
20 |
d->write_count -= count; |
766 |
|
|
d->write_offset += 512 * count; |
767 |
dpavlin |
4 |
|
768 |
dpavlin |
34 |
d->int_assert = 1; |
769 |
dpavlin |
4 |
|
770 |
|
|
if (d->write_count == 0) |
771 |
|
|
d->write_in_progress = 0; |
772 |
dpavlin |
24 |
|
773 |
|
|
free(buf); |
774 |
dpavlin |
4 |
} |
775 |
|
|
} |
776 |
|
|
break; |
777 |
|
|
|
778 |
|
|
case wd_error: /* 1: error (r), precomp (w) */ |
779 |
dpavlin |
20 |
if (writeflag == MEM_READ) { |
780 |
dpavlin |
4 |
odata = d->error; |
781 |
dpavlin |
22 |
debug("[ wdc: read from ERROR: 0x%02x ]\n", (int)odata); |
782 |
dpavlin |
4 |
/* TODO: is the error value cleared on read? */ |
783 |
|
|
d->error = 0; |
784 |
|
|
} else { |
785 |
|
|
d->precomp = idata; |
786 |
dpavlin |
14 |
debug("[ wdc: write to PRECOMP: 0x%02x ]\n",(int)idata); |
787 |
dpavlin |
4 |
} |
788 |
|
|
break; |
789 |
|
|
|
790 |
dpavlin |
20 |
case wd_seccnt: /* 2: sector count (or "ireason" for ATAPI) */ |
791 |
|
|
if (writeflag == MEM_READ) { |
792 |
dpavlin |
4 |
odata = d->seccnt; |
793 |
dpavlin |
20 |
if (d->atapi_cmd_in_progress) { |
794 |
|
|
odata = d->atapi_phase & (WDCI_CMD | WDCI_IN); |
795 |
|
|
} |
796 |
dpavlin |
14 |
debug("[ wdc: read from SECCNT: 0x%02x ]\n",(int)odata); |
797 |
dpavlin |
4 |
} else { |
798 |
|
|
d->seccnt = idata; |
799 |
dpavlin |
14 |
debug("[ wdc: write to SECCNT: 0x%02x ]\n", (int)idata); |
800 |
dpavlin |
4 |
} |
801 |
|
|
break; |
802 |
|
|
|
803 |
|
|
case wd_sector: /* 3: first sector */ |
804 |
dpavlin |
20 |
if (writeflag == MEM_READ) { |
805 |
dpavlin |
4 |
odata = d->sector; |
806 |
dpavlin |
14 |
debug("[ wdc: read from SECTOR: 0x%02x ]\n",(int)odata); |
807 |
dpavlin |
4 |
} else { |
808 |
|
|
d->sector = idata; |
809 |
dpavlin |
14 |
debug("[ wdc: write to SECTOR: 0x%02x ]\n", (int)idata); |
810 |
dpavlin |
4 |
} |
811 |
|
|
break; |
812 |
|
|
|
813 |
|
|
case wd_cyl_lo: /* 4: cylinder low */ |
814 |
dpavlin |
20 |
if (writeflag == MEM_READ) { |
815 |
dpavlin |
4 |
odata = d->cyl_lo; |
816 |
dpavlin |
20 |
if (d->cur_command == COMMAND_RESET && |
817 |
|
|
diskimage_is_a_cdrom(cpu->machine, |
818 |
|
|
d->drive + d->base_drive, DISKIMAGE_IDE)) |
819 |
|
|
odata = 0x14; |
820 |
|
|
if (d->atapi_cmd_in_progress) { |
821 |
|
|
int x = d->atapi_len; |
822 |
|
|
if (x > 32768) |
823 |
|
|
x = 32768; |
824 |
|
|
odata = x & 255; |
825 |
|
|
} |
826 |
dpavlin |
14 |
debug("[ wdc: read from CYL_LO: 0x%02x ]\n",(int)odata); |
827 |
dpavlin |
4 |
} else { |
828 |
|
|
d->cyl_lo = idata; |
829 |
dpavlin |
14 |
debug("[ wdc: write to CYL_LO: 0x%02x ]\n", (int)idata); |
830 |
dpavlin |
4 |
} |
831 |
|
|
break; |
832 |
|
|
|
833 |
dpavlin |
20 |
case wd_cyl_hi: /* 5: cylinder high */ |
834 |
|
|
if (writeflag == MEM_READ) { |
835 |
dpavlin |
4 |
odata = d->cyl_hi; |
836 |
dpavlin |
20 |
if (d->cur_command == COMMAND_RESET && |
837 |
|
|
diskimage_is_a_cdrom(cpu->machine, |
838 |
|
|
d->drive + d->base_drive, DISKIMAGE_IDE)) |
839 |
|
|
odata = 0xeb; |
840 |
|
|
if (d->atapi_cmd_in_progress) { |
841 |
|
|
int x = d->atapi_len; |
842 |
|
|
if (x > 32768) |
843 |
|
|
x = 32768; |
844 |
|
|
odata = (x >> 8) & 255; |
845 |
|
|
} |
846 |
dpavlin |
14 |
debug("[ wdc: read from CYL_HI: 0x%02x ]\n",(int)odata); |
847 |
dpavlin |
4 |
} else { |
848 |
|
|
d->cyl_hi = idata; |
849 |
dpavlin |
14 |
debug("[ wdc: write to CYL_HI: 0x%02x ]\n", (int)idata); |
850 |
dpavlin |
4 |
} |
851 |
|
|
break; |
852 |
|
|
|
853 |
|
|
case wd_sdh: /* 6: sectorsize/drive/head */ |
854 |
|
|
if (writeflag==MEM_READ) { |
855 |
|
|
odata = (d->sectorsize << 6) + (d->lba << 5) + |
856 |
|
|
(d->drive << 4) + (d->head); |
857 |
|
|
debug("[ wdc: read from SDH: 0x%02x (sectorsize %i," |
858 |
|
|
" lba=%i, drive %i, head %i) ]\n", (int)odata, |
859 |
|
|
d->sectorsize, d->lba, d->drive, d->head); |
860 |
|
|
} else { |
861 |
|
|
d->sectorsize = (idata >> 6) & 3; |
862 |
|
|
d->lba = (idata >> 5) & 1; |
863 |
|
|
d->drive = (idata >> 4) & 1; |
864 |
|
|
d->head = idata & 0xf; |
865 |
|
|
debug("[ wdc: write to SDH: 0x%02x (sectorsize %i," |
866 |
|
|
" lba=%i, drive %i, head %i) ]\n", (int)idata, |
867 |
|
|
d->sectorsize, d->lba, d->drive, d->head); |
868 |
|
|
} |
869 |
|
|
break; |
870 |
|
|
|
871 |
|
|
case wd_command: /* 7: command or status */ |
872 |
|
|
if (writeflag==MEM_READ) { |
873 |
|
|
odata = status_byte(d, cpu); |
874 |
dpavlin |
6 |
if (!quiet_mode) |
875 |
|
|
debug("[ wdc: read from STATUS: 0x%02x ]\n", |
876 |
dpavlin |
14 |
(int)odata); |
877 |
dpavlin |
34 |
INTERRUPT_DEASSERT(d->irq); |
878 |
|
|
d->int_assert = 0; |
879 |
dpavlin |
4 |
} else { |
880 |
dpavlin |
14 |
debug("[ wdc: write to COMMAND: 0x%02x ]\n",(int)idata); |
881 |
dpavlin |
20 |
wdc_command(cpu, d, idata); |
882 |
dpavlin |
4 |
} |
883 |
|
|
break; |
884 |
|
|
|
885 |
|
|
default: |
886 |
|
|
if (writeflag==MEM_READ) |
887 |
|
|
debug("[ wdc: read from 0x%02x ]\n", |
888 |
|
|
(int)relative_addr); |
889 |
|
|
else |
890 |
|
|
debug("[ wdc: write to 0x%02x: 0x%02x ]\n", |
891 |
|
|
(int)relative_addr, (int)idata); |
892 |
|
|
} |
893 |
|
|
|
894 |
dpavlin |
34 |
/* Assert interrupt, if necessary: */ |
895 |
|
|
dev_wdc_tick(cpu, extra); |
896 |
dpavlin |
30 |
|
897 |
|
|
ret: |
898 |
dpavlin |
18 |
if (writeflag == MEM_READ) { |
899 |
|
|
if (relative_addr == wd_data) |
900 |
|
|
memory_writemax64(cpu, data, len, odata); |
901 |
|
|
else |
902 |
|
|
data[0] = odata; |
903 |
|
|
} |
904 |
|
|
|
905 |
dpavlin |
4 |
return 1; |
906 |
|
|
} |
907 |
|
|
|
908 |
|
|
|
909 |
dpavlin |
22 |
DEVINIT(wdc) |
910 |
dpavlin |
4 |
{ |
911 |
|
|
struct wdc_data *d; |
912 |
|
|
uint64_t alt_status_addr; |
913 |
dpavlin |
18 |
int i, tick_shift = WDC_TICK_SHIFT; |
914 |
dpavlin |
4 |
|
915 |
dpavlin |
42 |
CHECK_ALLOCATION(d = malloc(sizeof(struct wdc_data))); |
916 |
dpavlin |
4 |
memset(d, 0, sizeof(struct wdc_data)); |
917 |
dpavlin |
34 |
|
918 |
|
|
INTERRUPT_CONNECT(devinit->interrupt_path, d->irq); |
919 |
dpavlin |
22 |
d->addr_mult = devinit->addr_mult; |
920 |
dpavlin |
20 |
d->data_debug = 1; |
921 |
dpavlin |
30 |
d->io_enabled = 1; |
922 |
dpavlin |
20 |
|
923 |
|
|
d->inbuf = zeroed_alloc(WDC_INBUF_SIZE); |
924 |
|
|
|
925 |
dpavlin |
14 |
/* base_drive = 0 for the primary controller, 2 for the secondary. */ |
926 |
|
|
d->base_drive = 0; |
927 |
|
|
if ((devinit->addr & 0xfff) == 0x170) |
928 |
|
|
d->base_drive = 2; |
929 |
dpavlin |
4 |
|
930 |
dpavlin |
14 |
alt_status_addr = devinit->addr + 0x206; |
931 |
|
|
|
932 |
dpavlin |
22 |
/* Special hacks for individual machines: */ |
933 |
|
|
switch (devinit->machine->machine_type) { |
934 |
|
|
case MACHINE_MACPPC: |
935 |
|
|
alt_status_addr = devinit->addr + 0x160; |
936 |
|
|
break; |
937 |
|
|
case MACHINE_HPCMIPS: |
938 |
|
|
/* TODO: Fix */ |
939 |
|
|
if (devinit->addr == 0x14000180) |
940 |
|
|
alt_status_addr = 0x14000386; |
941 |
|
|
break; |
942 |
|
|
case MACHINE_IQ80321: |
943 |
|
|
alt_status_addr = devinit->addr + 0x402; |
944 |
|
|
break; |
945 |
|
|
} |
946 |
dpavlin |
4 |
|
947 |
dpavlin |
14 |
/* Get disk geometries: */ |
948 |
|
|
for (i=0; i<2; i++) |
949 |
|
|
if (diskimage_exist(devinit->machine, d->base_drive +i, |
950 |
|
|
DISKIMAGE_IDE)) |
951 |
|
|
diskimage_getchs(devinit->machine, d->base_drive + i, |
952 |
|
|
DISKIMAGE_IDE, &d->cyls[i], &d->heads[i], |
953 |
|
|
&d->sectors_per_track[i]); |
954 |
dpavlin |
4 |
|
955 |
dpavlin |
14 |
memory_device_register(devinit->machine->memory, "wdc_altstatus", |
956 |
dpavlin |
20 |
alt_status_addr, 2, dev_wdc_altstatus_access, d, DM_DEFAULT, NULL); |
957 |
dpavlin |
14 |
memory_device_register(devinit->machine->memory, devinit->name, |
958 |
dpavlin |
22 |
devinit->addr, DEV_WDC_LENGTH * devinit->addr_mult, dev_wdc_access, |
959 |
|
|
d, DM_DEFAULT, NULL); |
960 |
dpavlin |
14 |
|
961 |
|
|
machine_add_tickfunction(devinit->machine, dev_wdc_tick, |
962 |
dpavlin |
42 |
d, tick_shift); |
963 |
dpavlin |
14 |
|
964 |
dpavlin |
30 |
devinit->return_ptr = d; |
965 |
|
|
|
966 |
dpavlin |
14 |
return 1; |
967 |
dpavlin |
4 |
} |
968 |
|
|
|