/[gxemul]/trunk/src/devices/dev_scc.c
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Revision 34 - (hide annotations)
Mon Oct 8 16:21:17 2007 UTC (16 years, 7 months ago) by dpavlin
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File size: 13576 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1480 2007/02/19 01:34:42 debug Exp $
20061029	Changing usleep(1) calls in the debugger to usleep(10000)
20061107	Adding a new disk image option (-d o...) which sets the ISO9660
		filesystem base offset; also making some other hacks to allow
		NetBSD/dreamcast and homebrew demos/games to boot directly
		from a filesystem image.
		Moving Dreamcast-specific stuff in the documentation to its
		own page (dreamcast.html).
		Adding a border to the Dreamcast PVR framebuffer.
20061108	Adding a -T command line option (again?), for halting the
		emulator on unimplemented memory accesses.
20061109	Continuing on various SH4 and Dreamcast related things.
		The emulator should now halt on more unimplemented device
		accesses, instead of just printing a warning, forcing me to
		actually implement missing stuff :)
20061111	Continuing on SH4 and Dreamcast stuff.
		Adding a bogus Landisk (SH4) machine mode.
20061112	Implementing some parts of the Dreamcast GDROM device. With
		some ugly hacks, NetBSD can (barely) mount an ISO image.
20061113	NetBSD/dreamcast now starts booting from the Live CD image,
		but crashes randomly quite early on in the boot process.
20061122	Beginning on a skeleton interrupt.h and interrupt.c for the
		new interrupt subsystem.
20061124	Continuing on the new interrupt system; taking the first steps
		to attempt to connect CPUs (SuperH and MIPS) and devices
		(dev_cons and SH4 timer interrupts) to it. Many things will
		probably break from now on.
20061125	Converting dev_ns16550, dev_8253 to the new interrupt system.
		Attempting to begin to convert the ISA bus.
20061130	Incorporating a patch from Brian Foley for the configure
		script, which checks for X11 libs in /usr/X11R6/lib64 (which
		is used on some Linux systems).
20061227	Adding a note in the man page about booting from Dreamcast
		CDROM images (i.e. that no external kernel is needed).
20061229	Continuing on the interrupt system rewrite: beginning to
		convert more devices, adding abort() calls for legacy interrupt
		system calls so that everything now _has_ to be rewritten!
		Almost all machine modes are now completely broken.
20061230	More progress on removing old interrupt code, mostly related
		to the ISA bus + devices, the LCA bus (on AlphaBook1), and
		the Footbridge bus (for CATS). And some minor PCI stuff.
		Connecting the ARM cpu to the new interrupt system.
		The CATS, NetWinder, and QEMU_MIPS machine modes now work with
		the new interrupt system :)
20061231	Connecting PowerPC CPUs to the new interrupt system.
		Making PReP machines (IBM 6050) work again.
		Beginning to convert the GT PCI controller (for e.g. Malta
		and Cobalt emulation). Some things work, but not everything.
		Updating Copyright notices for 2007.
20070101	Converting dev_kn02 from legacy style to devinit; the 3max
		machine mode now works with the new interrupt system :-]
20070105	Beginning to convert the SGI O2 machine to the new interrupt
		system; finally converting O2 (IP32) devices to devinit, etc.
20070106	Continuing on the interrupt system redesign/rewrite; KN01
		(PMAX), KN230, and Dreamcast ASIC interrupts should work again,
		moving out stuff from machine.h and devices.h into the
		corresponding devices, beginning the rewrite of i80321
		interrupts, etc.
20070107	Beginning on the rewrite of Eagle interrupt stuff (PReP, etc).
20070117	Beginning the rewrite of Algor (V3) interrupts (finally
		changing dev_v3 into devinit style).
20070118	Removing the "bus" registry concept from machine.h, because
		it was practically meaningless.
		Continuing on the rewrite of Algor V3 ISA interrupts.
20070121	More work on Algor interrupts; they are now working again,
		well enough to run NetBSD/algor. :-)
20070122	Converting VR41xx (HPCmips) interrupts. NetBSD/hpcmips
		can be installed using the new interrupt system :-)
20070123	Making the testmips mode work with the new interrupt system.
20070127	Beginning to convert DEC5800 devices to devinit, and to the
		new interrupt system.
		Converting Playstation 2 devices to devinit, and converting
		the interrupt system. Also fixing a severe bug: the interrupt
		mask register on Playstation 2 is bitwise _toggled_ on writes.
20070128	Removing the dummy NetGear machine mode and the 8250 device
		(which was only used by the NetGear machine).
		Beginning to convert the MacPPC GC (Grand Central) interrupt
		controller to the new interrupt system.
		Converting Jazz interrupts (PICA61 etc.) to the new interrupt
		system. NetBSD/arc can be installed again :-)
		Fixing the JAZZ timer (hardcoding it at 100 Hz, works with
		NetBSD and it is better than a completely dummy timer as it
		was before).
		Converting dev_mp to the new interrupt system, although I
		haven't had time to actually test it yet.
		Completely removing src/machines/interrupts.c, cpu_interrupt
		and cpu_interrupt_ack in src/cpu.c, and
		src/include/machine_interrupts.h! Adding fatal error messages
		+ abort() in the few places that are left to fix.
		Converting dev_z8530 to the new interrupt system.
		FINALLY removing the md_int struct completely from the
		machine struct.
		SH4 fixes (adding a PADDR invalidation in the ITLB replacement
		code in memory_sh.c); the NetBSD/dreamcast LiveCD now runs
		all the way to the login prompt, and can be interacted with :-)
		Converting the CPC700 controller (PCI and interrupt controller
		for PM/PPC) to the new interrupt system.
20070129	Fixing MACE ISA interrupts (SGI IP32 emulation). Both NetBSD/
		sgimips' and OpenBSD/sgi's ramdisk kernels can now be
		interacted with again.
20070130	Moving out the MIPS multi_lw and _sw instruction combinations
		so that they are auto-generated at compile time instead.
20070131	Adding detection of amd64/x86_64 hosts in the configure script,
		for doing initial experiments (again :-) with native code
		generation.
		Adding a -k command line option to set the size of the dyntrans
		cache, and a -B command line option to disable native code
		generation, even if GXemul was compiled with support for
		native code generation for the specific host CPU architecture.
20070201	Experimenting with a skeleton for native code generation.
		Changing the default behaviour, so that native code generation
		is now disabled by default, and has to be enabled by using
		-b on the command line.
20070202	Continuing the native code generation experiments.
		Making PCI interrupts work for Footbridge again.
20070203	More native code generation experiments.
		Removing most of the native code generation experimental code,
		it does not make sense to include any quick hacks like this.
		Minor cleanup/removal of some more legacy MIPS interrupt code.
20070204	Making i80321 interrupts work again (for NetBSD/evbarm etc.),
		and fixing the timer at 100 Hz.
20070206	Experimenting with removing the wdc interrupt slowness hack.
20070207	Lowering the number of dyntrans TLB entries for MIPS from
		192 to 128, resulting in a minor speed improvement.
		Minor optimization to the code invalidation routine in
		cpu_dyntrans.c.
20070208	Increasing (experimentally) the nr of dyntrans instructions per
		loop from 60 to 120.
20070210	Commenting out (experimentally) the dyntrans_device_danger
		detection in memory_rw.c.
		Changing the testmips and baremips machines to use a revision 2
		MIPS64 CPU by default, instead of revision 1.
		Removing the dummy i960, IA64, x86, AVR32, and HP PA-RISC
		files, the PC bios emulation, and the Olivetti M700 (ARC) and
		db64360 emulation modes.
20070211	Adding an "mp" demo to the demos directory, which tests the
		SMP functionality of the testmips machine.
		Fixing PReP interrupts some more. NetBSD/prep now boots again.
20070216	Adding a "nop workaround" for booting Mach/PMAX to the
		documentation; thanks to Artur Bujdoso for the values.
		Converting more of the MacPPC interrupt stuff to the new
		system.
		Beginning to convert BeBox interrupts to the new system.
		PPC603e should NOT have the PPC_NO_DEC flag! Removing it.
		Correcting BeBox clock speed (it was set to 100 in the NetBSD
		bootinfo block, but should be 33000000/4), allowing NetBSD
		to start without using the (incorrect) PPC_NO_DEC hack.
20070217	Implementing (slow) AltiVec vector loads and stores, allowing
		NetBSD/macppc to finally boot using the GENERIC kernel :-)
		Updating the documentation with install instructions for
		NetBSD/macppc.
20070218-19	Regression testing for the release.

==============  RELEASE 0.4.4  ==============


1 dpavlin 4 /*
2 dpavlin 34 * Copyright (C) 2003-2007 Anders Gavare. All rights reserved.
3 dpavlin 4 *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28 dpavlin 34 * $Id: dev_scc.c,v 1.37 2007/01/28 14:15:30 debug Exp $
29 dpavlin 4 *
30     * Serial controller on some DECsystems and SGI machines. (Z8530 ?)
31     * Most of the code in here is written for DECsystem emulation, though.
32     *
33     * NOTE:
34     * Each scc device is responsible for two lines; the first scc device
35     * controls mouse (0) and keyboard (1), and the second device controls
36     * serial ports (2 and 3).
37     *
38     * TODO:
39     * Mouse support!!! (scc0 and scc1 need to cooperate, in order to
40     * emulate the same lk201 behaviour as when using the dc device)
41     * DMA
42     * More correct interrupt support.
43 dpavlin 22 *
44     ******************************************************************************
45     * _____ ___ ____ ___ _
46     * |_ _/ _ \| _ \ / _ \| |
47     * | || | | | | | | | | | |
48     * | || |_| | |_| | |_| |_|
49     * |_| \___/|____/ \___/(_)
50     *
51     * Since this is actually a Z8530, it should be merged with dev_z8530.c!
52 dpavlin 4 */
53    
54     #include <stdio.h>
55     #include <stdlib.h>
56     #include <string.h>
57    
58     #include "console.h"
59     #include "cpu.h"
60     #include "devices.h"
61     #include "machine.h"
62     #include "memory.h"
63     #include "misc.h"
64    
65     #include "sccreg.h"
66    
67    
68     #define SCC_TICK_SHIFT 14
69    
70     #define N_SCC_PORTS 2
71     #define N_SCC_REGS 16
72     #define MAX_QUEUE_LEN 1024
73    
74     /* #define SCC_DEBUG */
75    
76    
77     struct scc_data {
78     int irq_nr;
79     int use_fb;
80     int console_handle;
81    
82     int scc_nr;
83     int addrmul;
84    
85     int register_select_in_progress[N_SCC_PORTS];
86     int register_selected[N_SCC_PORTS];
87    
88     unsigned char scc_register_r[N_SCC_PORTS * N_SCC_REGS];
89     unsigned char scc_register_w[N_SCC_PORTS * N_SCC_REGS];
90    
91     unsigned char rx_queue_char[N_SCC_PORTS * MAX_QUEUE_LEN];
92     int cur_rx_queue_pos_write[N_SCC_PORTS];
93     int cur_rx_queue_pos_read[N_SCC_PORTS];
94    
95     struct lk201_data lk201;
96     };
97    
98    
99     /*
100     * dev_scc_add_to_rx_queue():
101     *
102     * Add a character to the receive queue.
103     */
104     void dev_scc_add_to_rx_queue(void *e, int ch, int portnr)
105     {
106     struct scc_data *d = (struct scc_data *) e;
107     int scc_nr;
108    
109     /* DC's keyboard port ==> SCC keyboard port */
110     if (portnr == 0)
111     portnr = 3;
112    
113     scc_nr = portnr / N_SCC_PORTS;
114     if (scc_nr != d->scc_nr)
115     return;
116    
117     portnr &= (N_SCC_PORTS - 1);
118    
119     d->rx_queue_char[portnr * MAX_QUEUE_LEN +
120     d->cur_rx_queue_pos_write[portnr]] = ch;
121     d->cur_rx_queue_pos_write[portnr] ++;
122     if (d->cur_rx_queue_pos_write[portnr] == MAX_QUEUE_LEN)
123     d->cur_rx_queue_pos_write[portnr] = 0;
124    
125     if (d->cur_rx_queue_pos_write[portnr] ==
126     d->cur_rx_queue_pos_read[portnr])
127     fatal("warning: add_to_rx_queue(): rx_queue overrun!\n");
128     }
129    
130    
131     static int rx_avail(struct scc_data *d, int portnr)
132     {
133     return d->cur_rx_queue_pos_write[portnr] !=
134     d->cur_rx_queue_pos_read[portnr];
135     }
136    
137    
138     static unsigned char rx_nextchar(struct scc_data *d, int portnr)
139     {
140     unsigned char ch;
141     ch = d->rx_queue_char[portnr * MAX_QUEUE_LEN +
142     d->cur_rx_queue_pos_read[portnr]];
143     d->cur_rx_queue_pos_read[portnr]++;
144     if (d->cur_rx_queue_pos_read[portnr] == MAX_QUEUE_LEN)
145     d->cur_rx_queue_pos_read[portnr] = 0;
146     return ch;
147     }
148    
149    
150 dpavlin 30 DEVICE_TICK(scc)
151 dpavlin 4 {
152     int i;
153     struct scc_data *d = (struct scc_data *) extra;
154    
155     /* Add keystrokes to the rx queue: */
156     if (d->use_fb == 0 && d->scc_nr == 1) {
157     if (console_charavail(d->console_handle))
158     dev_scc_add_to_rx_queue(extra, console_readchar(
159     d->console_handle), 2);
160     }
161     if (d->use_fb == 1 && d->scc_nr == 1)
162 dpavlin 32 lk201_tick(cpu->machine, &d->lk201);
163 dpavlin 4
164     for (i=0; i<N_SCC_PORTS; i++) {
165     d->scc_register_r[i * N_SCC_REGS + SCC_RR0] |= SCC_RR0_TX_EMPTY;
166     d->scc_register_r[i * N_SCC_REGS + SCC_RR1] = 0;
167     /* No receive errors */
168    
169     d->scc_register_r[i * N_SCC_REGS + SCC_RR0] &=
170     ~SCC_RR0_RX_AVAIL;
171     if (rx_avail(d, i))
172     d->scc_register_r[i * N_SCC_REGS + SCC_RR0] |=
173     SCC_RR0_RX_AVAIL;
174    
175     /*
176     * Interrupts:
177     * (NOTE: Interrupt enables are always at channel A)
178     */
179     if (d->scc_register_w[N_SCC_REGS + SCC_WR9] &
180     SCC_WR9_MASTER_IE) {
181     /* TX interrupts? */
182     if (d->scc_register_w[i * N_SCC_REGS + SCC_WR1] &
183     SCC_WR1_TX_IE) {
184     if (d->scc_register_r[i * N_SCC_REGS + SCC_RR3]
185     & SCC_RR3_TX_IP_A ||
186     d->scc_register_r[i * N_SCC_REGS + SCC_RR3]
187 dpavlin 34 & SCC_RR3_TX_IP_B) {
188     fatal("TODO: legacy rewrite!\n");
189     abort();
190     // cpu_interrupt(cpu, d->irq_nr);
191     }
192 dpavlin 4 }
193    
194     /* RX interrupts? */
195     if (d->scc_register_w[N_SCC_REGS + SCC_WR1] &
196     (SCC_WR1_RXI_FIRST_CHAR | SCC_WR1_RXI_ALL_CHAR)) {
197     if (d->scc_register_r[i * N_SCC_REGS + SCC_RR0]
198     & SCC_RR0_RX_AVAIL) {
199     if (i == SCC_CHANNEL_A)
200     d->scc_register_r[N_SCC_REGS +
201     SCC_RR3] |= SCC_RR3_RX_IP_A;
202     else
203     d->scc_register_r[N_SCC_REGS +
204     SCC_RR3] |= SCC_RR3_RX_IP_B;
205     }
206    
207     if (d->scc_register_r[i * N_SCC_REGS + SCC_RR3]
208     & SCC_RR3_RX_IP_A ||
209     d->scc_register_r[i * N_SCC_REGS + SCC_RR3]
210 dpavlin 34 & SCC_RR3_RX_IP_B) {
211     fatal("TODO: legacy rewrite!\n");
212     abort();
213     // cpu_interrupt(cpu, d->irq_nr);
214     }
215 dpavlin 4 }
216    
217     if (d->scc_register_w[N_SCC_REGS + SCC_WR1] &
218     SCC_WR1_DMA_MODE) {
219     if (d->scc_register_r[i * N_SCC_REGS + SCC_RR0]
220     & SCC_RR0_RX_AVAIL) {
221     if (i == SCC_CHANNEL_A)
222     d->scc_register_r[N_SCC_REGS +
223     SCC_RR3] |=
224     SCC_RR3_EXT_IP_A;
225     else
226     d->scc_register_r[N_SCC_REGS +
227     SCC_RR3] |=
228     SCC_RR3_EXT_IP_B;
229     }
230    
231     if (d->scc_register_r[i * N_SCC_REGS + SCC_RR3]
232     & SCC_RR3_EXT_IP_A ||
233     d->scc_register_r[i * N_SCC_REGS + SCC_RR3]
234     & SCC_RR3_EXT_IP_B)
235     {
236 dpavlin 34 fatal("TODO: legacy rewrite!\n");
237     abort();
238     // cpu_interrupt(cpu, d->irq_nr);
239 dpavlin 4 /* TODO: huh? */
240 dpavlin 34 //cpu_interrupt(cpu, 8 + 0x02000000);
241 dpavlin 4 }
242     }
243     }
244     }
245     }
246    
247    
248     /*
249     * dev_scc_dma_func():
250     */
251     int dev_scc_dma_func(struct cpu *cpu, void *extra, uint64_t addr,
252     size_t dma_len, int tx)
253     {
254     /* printf("dev_scc_dma_func(): addr = %08x, len = %i\n",
255     (int)addr, (int)dma_len); */
256     unsigned char word[4];
257     struct scc_data *d = (struct scc_data *) extra;
258     int n;
259    
260     int port = SCC_CHANNEL_A; /* TODO */
261    
262     if (tx) {
263     do {
264     cpu->memory_rw(cpu, cpu->mem, addr, &word[0],
265     sizeof(word), MEM_READ, NO_EXCEPTIONS | PHYSICAL);
266    
267     lk201_tx_data(&d->lk201, d->scc_nr * 2 + port, word[1]);
268     /* Loopback: */
269     if (d->scc_register_w[port * N_SCC_REGS + SCC_WR14]
270     & SCC_WR14_LOCAL_LOOPB)
271     dev_scc_add_to_rx_queue(d, word[1],
272     d->scc_nr * 2 + port);
273    
274     addr += sizeof(word);
275     } while ((addr & 0xffc) != 0);
276    
277     dev_scc_tick(cpu, extra);
278     return 1;
279     } else {
280     printf("dev_scc_dma_func(): addr = %08x, len = %i\n",
281     (int)addr, (int)dma_len);
282    
283    
284     /* TODO: all this is just nonsense */
285    
286     n = 0;
287     while (rx_avail(d, port)) {
288     word[0] = word[1] = word[2] = word[3] = 0;
289     word[0] = word[1] = word[2] = word[3] =
290     rx_nextchar(d, port);
291     n++;
292     cpu->memory_rw(cpu, cpu->mem, addr, &word[0],
293     sizeof(word), MEM_WRITE, NO_EXCEPTIONS | PHYSICAL);
294    
295     addr += sizeof(word);
296     /* Half-page? */
297     if ((addr & 0x7fc) == 0)
298     break;
299     }
300     dev_scc_tick(cpu, extra);
301     return n*4;
302     }
303     }
304    
305    
306 dpavlin 22 DEVICE_ACCESS(scc)
307 dpavlin 4 {
308     struct scc_data *d = (struct scc_data *) extra;
309     uint64_t idata = 0, odata = 0;
310     int port;
311     int ultrix_mode = 0;
312    
313 dpavlin 18 if (writeflag == MEM_WRITE)
314     idata = memory_readmax64(cpu, data, len);
315 dpavlin 4
316     /* relative_addr /= d->addrmul; */
317     /* See SGI comment below instead. */
318     /*
319     * SGI writes command to 0x0f, and data to 0x1f.
320     * (TODO: This works for port nr 0, how about port nr 1?)
321     */
322     if ((relative_addr & 0x0f) == 0xf) {
323     if (relative_addr == 0x0f)
324     relative_addr = 1;
325     else
326     relative_addr = 5;
327     }
328    
329     port = relative_addr / 8;
330     relative_addr &= 7;
331    
332     dev_scc_tick(cpu, extra);
333    
334     /*
335     * Ultrix writes words such as 0x1200 to relative address 0,
336     * instead of writing the byte 0x12 directly to address 1.
337     */
338     if ((relative_addr == 0 || relative_addr == 4) && (idata & 0xff) == 0) {
339     ultrix_mode = 1;
340     relative_addr ++;
341     idata >>= 8;
342     }
343    
344     switch (relative_addr) {
345     case 1: /* command */
346     if (writeflag==MEM_READ) {
347     odata = d->scc_register_r[port * N_SCC_REGS +
348     d->register_selected[port]];
349    
350     if (d->register_selected[port] == SCC_RR3) {
351     if (port == SCC_CHANNEL_B)
352     fatal("WARNING! scc channel B has "
353     "no RR3\n");
354    
355     d->scc_register_r[port * N_SCC_REGS +
356     SCC_RR3] = 0;
357 dpavlin 34
358     fatal("TODO: legacy rewrite!\n");
359     abort();
360     // cpu_interrupt_ack(cpu, d->irq_nr);
361 dpavlin 4 }
362    
363     #ifdef SCC_DEBUG
364     fatal("[ scc: port %i, register %i, read value "
365     "0x%02x ]\n", port, d->register_selected[port],
366     (int)odata);
367     #endif
368     d->register_select_in_progress[port] = 0;
369     d->register_selected[port] = 0;
370     /* debug("[ scc: (port %i) read from 0x%08lx ]\n",
371     port, (long)relative_addr); */
372     } else {
373     /* If no register is selected, then select one.
374     Otherwise, write to the selected register. */
375     if (d->register_select_in_progress[port] == 0) {
376     d->register_select_in_progress[port] = 1;
377     d->register_selected[port] = idata;
378     d->register_selected[port] &= (N_SCC_REGS-1);
379     } else {
380     d->scc_register_w[port * N_SCC_REGS +
381     d->register_selected[port]] = idata;
382     #ifdef SCC_DEBUG
383     fatal("[ scc: port %i, register %i, write "
384     "value 0x%02x ]\n", port,
385     d->register_selected[port], idata);
386     #endif
387    
388     d->scc_register_r[port * N_SCC_REGS +
389     SCC_RR12] = d->scc_register_w[port *
390     N_SCC_REGS + SCC_WR12];
391     d->scc_register_r[port * N_SCC_REGS +
392     SCC_RR13] = d->scc_register_w[port *
393     N_SCC_REGS + SCC_WR13];
394    
395     d->register_select_in_progress[port] = 0;
396     d->register_selected[port] = 0;
397     }
398     }
399     break;
400     case 5: /* data */
401     if (writeflag==MEM_READ) {
402     if (rx_avail(d, port))
403     odata = rx_nextchar(d, port);
404    
405     /* TODO: perhaps only clear the RX part of RR3? */
406     d->scc_register_r[N_SCC_REGS + SCC_RR3] = 0;
407    
408 dpavlin 34 fatal("TODO: legacy rewrite!\n");
409     abort();
410     // cpu_interrupt_ack(cpu, d->irq_nr);
411    
412 dpavlin 4 debug("[ scc: (port %i) read from 0x%08lx: 0x%02x ]\n",
413     port, (long)relative_addr, (int)odata);
414     } else {
415     /* debug("[ scc: (port %i) write to 0x%08lx: "
416     "0x%08x ]\n", port, (long)relative_addr,
417     (int)idata); */
418    
419     /* Send the character: */
420     lk201_tx_data(&d->lk201, d->scc_nr * 2 + port, idata);
421    
422     /* Loopback: */
423     if (d->scc_register_w[port * N_SCC_REGS + SCC_WR14]
424     & SCC_WR14_LOCAL_LOOPB)
425     dev_scc_add_to_rx_queue(d, idata, d->scc_nr
426     * 2 + port);
427    
428     /* TX interrupt: */
429     if (d->scc_register_w[port * N_SCC_REGS + SCC_WR9] &
430     SCC_WR9_MASTER_IE &&
431     d->scc_register_w[port * N_SCC_REGS + SCC_WR1] &
432     SCC_WR1_TX_IE) {
433     if (port == SCC_CHANNEL_A)
434     d->scc_register_r[N_SCC_REGS + SCC_RR3]
435     |= SCC_RR3_TX_IP_A;
436     else
437     d->scc_register_r[N_SCC_REGS + SCC_RR3]
438     |= SCC_RR3_TX_IP_B;
439     }
440    
441     dev_scc_tick(cpu, extra);
442     }
443     break;
444     default:
445     if (writeflag==MEM_READ) {
446     debug("[ scc: (port %i) read from 0x%08lx ]\n",
447     port, (long)relative_addr);
448     } else {
449     debug("[ scc: (port %i) write to 0x%08lx: 0x%08x ]\n",
450     port, (long)relative_addr, (int)idata);
451     }
452     }
453    
454     if (ultrix_mode && writeflag == MEM_READ) {
455     odata <<= 8;
456     }
457    
458     if (writeflag == MEM_READ)
459     memory_writemax64(cpu, data, len, odata);
460    
461     return 1;
462     }
463    
464    
465     /*
466     * dev_scc_init():
467     *
468     * use_fb = non-zero when using graphical console + keyboard
469     * scc_nr = 0 or 1
470     * addmul = 1 in most cases, 8 on SGI?
471     */
472     void *dev_scc_init(struct machine *machine, struct memory *mem,
473     uint64_t baseaddr, int irq_nr, int use_fb, int scc_nr, int addrmul)
474     {
475     struct scc_data *d;
476    
477     d = malloc(sizeof(struct scc_data));
478     if (d == NULL) {
479     fprintf(stderr, "out of memory\n");
480     exit(1);
481     }
482     memset(d, 0, sizeof(struct scc_data));
483     d->irq_nr = irq_nr;
484     d->scc_nr = scc_nr;
485     d->use_fb = use_fb;
486     d->addrmul = addrmul;
487 dpavlin 22 d->console_handle = console_start_slave(machine, "SCC", 1);
488 dpavlin 4
489     lk201_init(&d->lk201, use_fb, dev_scc_add_to_rx_queue,
490     d->console_handle, d);
491    
492     memory_device_register(mem, "scc", baseaddr, DEV_SCC_LENGTH,
493 dpavlin 20 dev_scc_access, d, DM_DEFAULT, NULL);
494 dpavlin 24 machine_add_tickfunction(machine, dev_scc_tick, d, SCC_TICK_SHIFT, 0.0);
495 dpavlin 4
496     return (void *) d;
497     }
498    

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