/[gxemul]/trunk/src/devices/dev_ps2_stuff.c
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Annotation of /trunk/src/devices/dev_ps2_stuff.c

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Revision 34 - (hide annotations)
Mon Oct 8 16:21:17 2007 UTC (16 years, 7 months ago) by dpavlin
File MIME type: text/plain
File size: 14153 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1480 2007/02/19 01:34:42 debug Exp $
20061029	Changing usleep(1) calls in the debugger to usleep(10000)
20061107	Adding a new disk image option (-d o...) which sets the ISO9660
		filesystem base offset; also making some other hacks to allow
		NetBSD/dreamcast and homebrew demos/games to boot directly
		from a filesystem image.
		Moving Dreamcast-specific stuff in the documentation to its
		own page (dreamcast.html).
		Adding a border to the Dreamcast PVR framebuffer.
20061108	Adding a -T command line option (again?), for halting the
		emulator on unimplemented memory accesses.
20061109	Continuing on various SH4 and Dreamcast related things.
		The emulator should now halt on more unimplemented device
		accesses, instead of just printing a warning, forcing me to
		actually implement missing stuff :)
20061111	Continuing on SH4 and Dreamcast stuff.
		Adding a bogus Landisk (SH4) machine mode.
20061112	Implementing some parts of the Dreamcast GDROM device. With
		some ugly hacks, NetBSD can (barely) mount an ISO image.
20061113	NetBSD/dreamcast now starts booting from the Live CD image,
		but crashes randomly quite early on in the boot process.
20061122	Beginning on a skeleton interrupt.h and interrupt.c for the
		new interrupt subsystem.
20061124	Continuing on the new interrupt system; taking the first steps
		to attempt to connect CPUs (SuperH and MIPS) and devices
		(dev_cons and SH4 timer interrupts) to it. Many things will
		probably break from now on.
20061125	Converting dev_ns16550, dev_8253 to the new interrupt system.
		Attempting to begin to convert the ISA bus.
20061130	Incorporating a patch from Brian Foley for the configure
		script, which checks for X11 libs in /usr/X11R6/lib64 (which
		is used on some Linux systems).
20061227	Adding a note in the man page about booting from Dreamcast
		CDROM images (i.e. that no external kernel is needed).
20061229	Continuing on the interrupt system rewrite: beginning to
		convert more devices, adding abort() calls for legacy interrupt
		system calls so that everything now _has_ to be rewritten!
		Almost all machine modes are now completely broken.
20061230	More progress on removing old interrupt code, mostly related
		to the ISA bus + devices, the LCA bus (on AlphaBook1), and
		the Footbridge bus (for CATS). And some minor PCI stuff.
		Connecting the ARM cpu to the new interrupt system.
		The CATS, NetWinder, and QEMU_MIPS machine modes now work with
		the new interrupt system :)
20061231	Connecting PowerPC CPUs to the new interrupt system.
		Making PReP machines (IBM 6050) work again.
		Beginning to convert the GT PCI controller (for e.g. Malta
		and Cobalt emulation). Some things work, but not everything.
		Updating Copyright notices for 2007.
20070101	Converting dev_kn02 from legacy style to devinit; the 3max
		machine mode now works with the new interrupt system :-]
20070105	Beginning to convert the SGI O2 machine to the new interrupt
		system; finally converting O2 (IP32) devices to devinit, etc.
20070106	Continuing on the interrupt system redesign/rewrite; KN01
		(PMAX), KN230, and Dreamcast ASIC interrupts should work again,
		moving out stuff from machine.h and devices.h into the
		corresponding devices, beginning the rewrite of i80321
		interrupts, etc.
20070107	Beginning on the rewrite of Eagle interrupt stuff (PReP, etc).
20070117	Beginning the rewrite of Algor (V3) interrupts (finally
		changing dev_v3 into devinit style).
20070118	Removing the "bus" registry concept from machine.h, because
		it was practically meaningless.
		Continuing on the rewrite of Algor V3 ISA interrupts.
20070121	More work on Algor interrupts; they are now working again,
		well enough to run NetBSD/algor. :-)
20070122	Converting VR41xx (HPCmips) interrupts. NetBSD/hpcmips
		can be installed using the new interrupt system :-)
20070123	Making the testmips mode work with the new interrupt system.
20070127	Beginning to convert DEC5800 devices to devinit, and to the
		new interrupt system.
		Converting Playstation 2 devices to devinit, and converting
		the interrupt system. Also fixing a severe bug: the interrupt
		mask register on Playstation 2 is bitwise _toggled_ on writes.
20070128	Removing the dummy NetGear machine mode and the 8250 device
		(which was only used by the NetGear machine).
		Beginning to convert the MacPPC GC (Grand Central) interrupt
		controller to the new interrupt system.
		Converting Jazz interrupts (PICA61 etc.) to the new interrupt
		system. NetBSD/arc can be installed again :-)
		Fixing the JAZZ timer (hardcoding it at 100 Hz, works with
		NetBSD and it is better than a completely dummy timer as it
		was before).
		Converting dev_mp to the new interrupt system, although I
		haven't had time to actually test it yet.
		Completely removing src/machines/interrupts.c, cpu_interrupt
		and cpu_interrupt_ack in src/cpu.c, and
		src/include/machine_interrupts.h! Adding fatal error messages
		+ abort() in the few places that are left to fix.
		Converting dev_z8530 to the new interrupt system.
		FINALLY removing the md_int struct completely from the
		machine struct.
		SH4 fixes (adding a PADDR invalidation in the ITLB replacement
		code in memory_sh.c); the NetBSD/dreamcast LiveCD now runs
		all the way to the login prompt, and can be interacted with :-)
		Converting the CPC700 controller (PCI and interrupt controller
		for PM/PPC) to the new interrupt system.
20070129	Fixing MACE ISA interrupts (SGI IP32 emulation). Both NetBSD/
		sgimips' and OpenBSD/sgi's ramdisk kernels can now be
		interacted with again.
20070130	Moving out the MIPS multi_lw and _sw instruction combinations
		so that they are auto-generated at compile time instead.
20070131	Adding detection of amd64/x86_64 hosts in the configure script,
		for doing initial experiments (again :-) with native code
		generation.
		Adding a -k command line option to set the size of the dyntrans
		cache, and a -B command line option to disable native code
		generation, even if GXemul was compiled with support for
		native code generation for the specific host CPU architecture.
20070201	Experimenting with a skeleton for native code generation.
		Changing the default behaviour, so that native code generation
		is now disabled by default, and has to be enabled by using
		-b on the command line.
20070202	Continuing the native code generation experiments.
		Making PCI interrupts work for Footbridge again.
20070203	More native code generation experiments.
		Removing most of the native code generation experimental code,
		it does not make sense to include any quick hacks like this.
		Minor cleanup/removal of some more legacy MIPS interrupt code.
20070204	Making i80321 interrupts work again (for NetBSD/evbarm etc.),
		and fixing the timer at 100 Hz.
20070206	Experimenting with removing the wdc interrupt slowness hack.
20070207	Lowering the number of dyntrans TLB entries for MIPS from
		192 to 128, resulting in a minor speed improvement.
		Minor optimization to the code invalidation routine in
		cpu_dyntrans.c.
20070208	Increasing (experimentally) the nr of dyntrans instructions per
		loop from 60 to 120.
20070210	Commenting out (experimentally) the dyntrans_device_danger
		detection in memory_rw.c.
		Changing the testmips and baremips machines to use a revision 2
		MIPS64 CPU by default, instead of revision 1.
		Removing the dummy i960, IA64, x86, AVR32, and HP PA-RISC
		files, the PC bios emulation, and the Olivetti M700 (ARC) and
		db64360 emulation modes.
20070211	Adding an "mp" demo to the demos directory, which tests the
		SMP functionality of the testmips machine.
		Fixing PReP interrupts some more. NetBSD/prep now boots again.
20070216	Adding a "nop workaround" for booting Mach/PMAX to the
		documentation; thanks to Artur Bujdoso for the values.
		Converting more of the MacPPC interrupt stuff to the new
		system.
		Beginning to convert BeBox interrupts to the new system.
		PPC603e should NOT have the PPC_NO_DEC flag! Removing it.
		Correcting BeBox clock speed (it was set to 100 in the NetBSD
		bootinfo block, but should be 33000000/4), allowing NetBSD
		to start without using the (incorrect) PPC_NO_DEC hack.
20070217	Implementing (slow) AltiVec vector loads and stores, allowing
		NetBSD/macppc to finally boot using the GENERIC kernel :-)
		Updating the documentation with install instructions for
		NetBSD/macppc.
20070218-19	Regression testing for the release.

==============  RELEASE 0.4.4  ==============
1 dpavlin 4 /*
2 dpavlin 34 * Copyright (C) 2003-2007 Anders Gavare. All rights reserved.
3 dpavlin 4 *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28 dpavlin 34 * $Id: dev_ps2_stuff.c,v 1.31 2007/02/16 16:48:07 debug Exp $
29 dpavlin 4 *
30     * Playstation 2 misc. stuff:
31     *
32     * offset 0x0000 timer control
33     * offset 0x8000 DMA controller
34     * offset 0xf000 Interrupt register
35 dpavlin 34 *
36     * The 16 normal PS2 interrupts interrupt at MIPS interrupt 2.
37     * The 16 DMA interrupts are connected to MIPS interrupt 3.
38     *
39     * SBUS interrupts go via PS2 interrupt 1.
40 dpavlin 4 */
41    
42     #include <stdio.h>
43     #include <stdlib.h>
44     #include <string.h>
45    
46     #include "cpu.h"
47 dpavlin 34 #include "device.h"
48 dpavlin 4 #include "machine.h"
49     #include "memory.h"
50     #include "misc.h"
51    
52     #include "ee_timerreg.h"
53     #include "ps2_dmacreg.h"
54    
55     #define TICK_STEPS_SHIFT 14
56    
57     /* NOTE/TODO: This should be the same as in ps2_gs: */
58     #define DEV_PS2_GIF_FAKE_BASE 0x50000000
59    
60 dpavlin 34 #define N_PS2_DMA_CHANNELS 10
61     #define N_PS2_TIMERS 4
62 dpavlin 4
63 dpavlin 34 struct ps2_data {
64     uint32_t timer_count[N_PS2_TIMERS];
65     uint32_t timer_comp[N_PS2_TIMERS];
66     uint32_t timer_mode[N_PS2_TIMERS];
67     uint32_t timer_hold[N_PS2_TIMERS];
68     /* NOTE: only 0 and 1 are valid */
69     struct interrupt timer_irq[N_PS2_TIMERS];
70    
71     uint64_t dmac_reg[DMAC_REGSIZE / 0x10];
72     struct interrupt dmac_irq; /* MIPS irq 3 */
73     struct interrupt dma_channel2_irq; /* irq path of channel 2 */
74    
75     uint64_t other_memory_base[N_PS2_DMA_CHANNELS];
76    
77     uint32_t intr;
78     uint32_t imask;
79     uint32_t sbus_smflg;
80     struct interrupt intr_irq; /* MIPS irq 2 */
81     struct interrupt sbus_irq; /* PS2 irq 1 */
82     };
83    
84     #define DEV_PS2_LENGTH 0x10000
85    
86    
87     void ps2_intr_interrupt_assert(struct interrupt *interrupt)
88 dpavlin 4 {
89 dpavlin 34 struct ps2_data *d = interrupt->extra;
90     d->intr |= (1 << interrupt->line);
91     if (d->intr & d->imask)
92     INTERRUPT_ASSERT(d->intr_irq);
93     }
94     void ps2_intr_interrupt_deassert(struct interrupt *interrupt)
95     {
96     struct ps2_data *d = interrupt->extra;
97     d->intr &= ~(1 << interrupt->line);
98     if (!(d->intr & d->imask))
99     INTERRUPT_DEASSERT(d->intr_irq);
100     }
101     void ps2_dmac_interrupt_assert(struct interrupt *interrupt)
102     {
103     struct ps2_data *d = interrupt->extra;
104     d->dmac_reg[0x601] |= (1 << interrupt->line);
105     /* TODO: DMA interrupt mask? */
106     if (d->dmac_reg[0x601] & 0xffff)
107     INTERRUPT_ASSERT(d->dmac_irq);
108     }
109     void ps2_dmac_interrupt_deassert(struct interrupt *interrupt)
110     {
111     struct ps2_data *d = interrupt->extra;
112     d->dmac_reg[0x601] &= ~(1 << interrupt->line);
113     /* TODO: DMA interrupt mask? */
114     if (!(d->dmac_reg[0x601] & 0xffff))
115     INTERRUPT_DEASSERT(d->dmac_irq);
116     }
117     void ps2_sbus_interrupt_assert(struct interrupt *interrupt)
118     {
119     /* Note: sbus irq 0 = mask 0x100, sbus irq 1 = mask 0x400 */
120     struct ps2_data *d = interrupt->extra;
121     d->sbus_smflg |= (1 << (8 + interrupt->line * 2));
122     /* TODO: SBUS interrupt mask? */
123     if (d->sbus_smflg != 0)
124     INTERRUPT_ASSERT(d->sbus_irq);
125     }
126     void ps2_sbus_interrupt_deassert(struct interrupt *interrupt)
127     {
128     /* Note: sbus irq 0 = mask 0x100, sbus irq 1 = mask 0x400 */
129     struct ps2_data *d = interrupt->extra;
130     d->sbus_smflg &= ~(1 << (8 + interrupt->line * 2));
131     /* TODO: SBUS interrupt mask? */
132     if (d->sbus_smflg == 0)
133     INTERRUPT_DEASSERT(d->sbus_irq);
134     }
135    
136    
137     DEVICE_TICK(ps2)
138     {
139 dpavlin 4 struct ps2_data *d = extra;
140     int i;
141    
142     /*
143     * Right now this interrupts every now and then.
144     * The main interrupt in NetBSD should be 100 Hz. TODO.
145     */
146     for (i=0; i<N_PS2_TIMERS; i++) {
147     /* Count-up Enable: TODO: by how much? */
148     if (d->timer_mode[i] & T_MODE_CUE)
149     d->timer_count[i] ++;
150    
151     if (d->timer_mode[i] & (T_MODE_CMPE | T_MODE_OVFE)) {
152     /* Zero return: */
153     if (d->timer_mode[i] & T_MODE_ZRET)
154     d->timer_count[i] = 0;
155    
156 dpavlin 34 INTERRUPT_ASSERT(d->timer_irq[i]);
157 dpavlin 4
158     /* timer 1..3 are "single-shot"? TODO */
159 dpavlin 22 if (i > 0) {
160     d->timer_mode[i] &=
161     ~(T_MODE_CMPE | T_MODE_OVFF);
162     }
163 dpavlin 4 }
164     }
165     }
166    
167    
168 dpavlin 34 DEVICE_ACCESS(ps2)
169 dpavlin 4 {
170     uint64_t idata = 0, odata = 0;
171     int regnr = 0;
172     struct ps2_data *d = extra;
173     int timer_nr = 0;
174    
175 dpavlin 18 if (writeflag == MEM_WRITE)
176     idata = memory_readmax64(cpu, data, len);
177 dpavlin 4
178     if (relative_addr >= 0x8000 && relative_addr < 0x8000 + DMAC_REGSIZE) {
179     regnr = (relative_addr - 0x8000) / 16;
180     if (writeflag == MEM_READ)
181     odata = d->dmac_reg[regnr];
182     else
183     d->dmac_reg[regnr] = idata;
184     }
185    
186     /*
187     * Timer control:
188     * The four timers are at offsets 0, 0x800, 0x1000, and 0x1800.
189     */
190     if (relative_addr < TIMER_REGSIZE) {
191     /* 0, 1, 2, or 3 */
192     timer_nr = (relative_addr & 0x1800) >> 11;
193     relative_addr &= (TIMER_OFS-1);
194     }
195    
196     switch (relative_addr) {
197     case 0x0000: /* timer count */
198     if (writeflag == MEM_READ) {
199     odata = d->timer_count[timer_nr];
200     if (timer_nr == 0) {
201     /* :-) TODO: remove this? */
202     d->timer_count[timer_nr] ++;
203     }
204 dpavlin 34 debug("[ ps2: read timer %i count: 0x%llx ]\n",
205 dpavlin 4 timer_nr, (long long)odata);
206     } else {
207     d->timer_count[timer_nr] = idata;
208 dpavlin 34 debug("[ ps2: write timer %i count: 0x%llx ]\n",
209 dpavlin 4 timer_nr, (long long)idata);
210     }
211     break;
212     case 0x0010: /* timer mode */
213     if (writeflag == MEM_READ) {
214     odata = d->timer_mode[timer_nr];
215 dpavlin 34 debug("[ ps2: read timer %i mode: 0x%llx ]\n",
216 dpavlin 4 timer_nr, (long long)odata);
217     } else {
218     d->timer_mode[timer_nr] = idata;
219 dpavlin 34 debug("[ ps2: write timer %i mode: 0x%llx ]\n",
220 dpavlin 4 timer_nr, (long long)idata);
221     }
222     break;
223     case 0x0020: /* timer comp */
224     if (writeflag == MEM_READ) {
225     odata = d->timer_comp[timer_nr];
226 dpavlin 34 debug("[ ps2: read timer %i comp: 0x%llx ]\n",
227 dpavlin 4 timer_nr, (long long)odata);
228     } else {
229     d->timer_comp[timer_nr] = idata;
230 dpavlin 34 debug("[ ps2: write timer %i comp: 0x%llx ]\n",
231 dpavlin 4 timer_nr, (long long)idata);
232     }
233     break;
234     case 0x0030: /* timer hold */
235     if (writeflag == MEM_READ) {
236     odata = d->timer_hold[timer_nr];
237 dpavlin 34 debug("[ ps2: read timer %i hold: 0x%llx ]\n",
238 dpavlin 4 timer_nr, (long long)odata);
239     if (timer_nr >= 2)
240 dpavlin 34 fatal("[ WARNING: ps2: read from non-"
241 dpavlin 4 "existant timer %i hold register ]\n");
242     } else {
243     d->timer_hold[timer_nr] = idata;
244 dpavlin 34 debug("[ ps2: write timer %i hold: 0x%llx ]\n",
245 dpavlin 4 timer_nr, (long long)idata);
246     if (timer_nr >= 2)
247 dpavlin 34 fatal("[ WARNING: ps2: write to "
248 dpavlin 4 "non-existant timer %i hold register ]\n",
249     timer_nr);
250     }
251     break;
252    
253     case 0x8000 + D2_CHCR_REG:
254     if (writeflag==MEM_READ) {
255     odata = d->dmac_reg[regnr];
256 dpavlin 34 /* debug("[ ps2: dmac read from D2_CHCR "
257 dpavlin 4 "(0x%llx) ]\n", (long long)d->dmac_reg[regnr]); */
258     } else {
259 dpavlin 34 /* debug("[ ps2: dmac write to D2_CHCR, "
260 dpavlin 4 "data 0x%016llx ]\n", (long long) idata); */
261     if (idata & D_CHCR_STR) {
262     int length = d->dmac_reg[D2_QWC_REG/0x10] * 16;
263     uint64_t from_addr = d->dmac_reg[
264     D2_MADR_REG/0x10];
265     uint64_t to_addr = d->dmac_reg[
266     D2_TADR_REG/0x10];
267     unsigned char *copy_buf;
268    
269 dpavlin 34 debug("[ ps2: dmac [ch2] transfer addr="
270 dpavlin 4 "0x%016llx len=0x%lx ]\n", (long long)
271     d->dmac_reg[D2_MADR_REG/0x10],
272     (long)length);
273    
274     copy_buf = malloc(length);
275     if (copy_buf == NULL) {
276     fprintf(stderr, "out of memory in "
277 dpavlin 34 "dev_ps2_access()\n");
278 dpavlin 4 exit(1);
279     }
280     cpu->memory_rw(cpu, cpu->mem, from_addr,
281     copy_buf, length, MEM_READ,
282     CACHE_NONE | PHYSICAL);
283     cpu->memory_rw(cpu, cpu->mem,
284     d->other_memory_base[DMA_CH_GIF] + to_addr,
285     copy_buf, length, MEM_WRITE,
286     CACHE_NONE | PHYSICAL);
287     free(copy_buf);
288    
289     /* Done with the transfer: */
290     d->dmac_reg[D2_QWC_REG/0x10] = 0;
291     idata &= ~D_CHCR_STR;
292    
293     /* interrupt DMA channel 2 */
294 dpavlin 34 INTERRUPT_ASSERT(d->dma_channel2_irq);
295 dpavlin 4 } else
296 dpavlin 34 debug("[ ps2: dmac [ch2] stopping "
297 dpavlin 4 "transfer ]\n");
298     d->dmac_reg[regnr] = idata;
299     return 1;
300     }
301     break;
302    
303     case 0x8000 + D2_QWC_REG:
304     case 0x8000 + D2_MADR_REG:
305     case 0x8000 + D2_TADR_REG:
306     /* no debug output */
307     break;
308    
309     case 0xe010: /* dmac interrupt status (and mask, */
310     /* the upper 16 bits) */
311     if (writeflag == MEM_WRITE) {
312     uint32_t oldmask = d->dmac_reg[regnr] & 0xffff0000;
313     /* Clear out those bits that are set in idata: */
314     d->dmac_reg[regnr] &= ~idata;
315     d->dmac_reg[regnr] &= 0xffff;
316     d->dmac_reg[regnr] |= oldmask;
317     if (((d->dmac_reg[regnr] & 0xffff) &
318     ((d->dmac_reg[regnr]>>16) & 0xffff)) == 0) {
319 dpavlin 34 INTERRUPT_DEASSERT(d->dmac_irq);
320 dpavlin 4 }
321     } else {
322     /* Hm... make it seem like the mask bits are (at
323     least as much as) the interrupt assertions: */
324     odata = d->dmac_reg[regnr];
325     odata |= (odata << 16);
326     }
327     break;
328    
329     case 0xf000: /* interrupt register */
330     if (writeflag == MEM_READ) {
331     odata = d->intr;
332 dpavlin 34 debug("[ ps2: read from Interrupt Register:"
333 dpavlin 4 " 0x%llx ]\n", (long long)odata);
334    
335     /* TODO: This is _NOT_ correct behavior: */
336 dpavlin 34 // d->intr = 0;
337     // INTERRUPT_DEASSERT(d->intr_irq);
338 dpavlin 4 } else {
339 dpavlin 34 debug("[ ps2: write to Interrupt Register: "
340 dpavlin 4 "0x%llx ]\n", (long long)idata);
341     /* Clear out bits that are set in idata: */
342     d->intr &= ~idata;
343    
344     if ((d->intr & d->imask) == 0)
345 dpavlin 34 INTERRUPT_DEASSERT(d->intr_irq);
346 dpavlin 4 }
347     break;
348    
349     case 0xf010: /* interrupt mask */
350     if (writeflag == MEM_READ) {
351     odata = d->imask;
352 dpavlin 34 /* debug("[ ps2: read from Interrupt Mask "
353 dpavlin 4 "Register: 0x%llx ]\n", (long long)odata); */
354     } else {
355 dpavlin 34 /* debug("[ ps2: write to Interrupt Mask "
356 dpavlin 4 "Register: 0x%llx ]\n", (long long)idata); */
357 dpavlin 34 /* Note: written value indicates which bits
358     to _toggle_, not which bits to set! */
359     d->imask ^= idata;
360 dpavlin 4 }
361     break;
362    
363     case 0xf230: /* sbus interrupt register? */
364     if (writeflag == MEM_READ) {
365     odata = d->sbus_smflg;
366 dpavlin 34 debug("[ ps2: read from SBUS SMFLG:"
367 dpavlin 4 " 0x%llx ]\n", (long long)odata);
368     } else {
369     /* Clear bits on write: */
370 dpavlin 34 debug("[ ps2: write to SBUS SMFLG:"
371 dpavlin 4 " 0x%llx ]\n", (long long)idata);
372     d->sbus_smflg &= ~idata;
373     /* irq 1 is SBUS */
374     if (d->sbus_smflg == 0)
375 dpavlin 34 INTERRUPT_DEASSERT(d->sbus_irq);
376 dpavlin 4 }
377     break;
378     default:
379     if (writeflag==MEM_READ) {
380 dpavlin 34 debug("[ ps2: read from addr 0x%x: 0x%llx ]\n",
381 dpavlin 4 (int)relative_addr, (long long)odata);
382     } else {
383 dpavlin 34 debug("[ ps2: write to addr 0x%x: 0x%llx ]\n",
384 dpavlin 4 (int)relative_addr, (long long)idata);
385     }
386     }
387    
388     if (writeflag == MEM_READ)
389     memory_writemax64(cpu, data, len, odata);
390    
391     return 1;
392     }
393    
394    
395 dpavlin 34 DEVINIT(ps2)
396 dpavlin 4 {
397     struct ps2_data *d;
398 dpavlin 34 int i;
399     struct interrupt template;
400     char n[300];
401 dpavlin 4
402     d = malloc(sizeof(struct ps2_data));
403     if (d == NULL) {
404     fprintf(stderr, "out of memory\n");
405     exit(1);
406     }
407     memset(d, 0, sizeof(struct ps2_data));
408    
409     d->other_memory_base[DMA_CH_GIF] = DEV_PS2_GIF_FAKE_BASE;
410    
411 dpavlin 34 /* Connect to MIPS irq 2 (interrupt controller) and 3 (dmac): */
412     snprintf(n, sizeof(n), "%s.2", devinit->interrupt_path);
413     INTERRUPT_CONNECT(n, d->intr_irq);
414     snprintf(n, sizeof(n), "%s.3", devinit->interrupt_path);
415     INTERRUPT_CONNECT(n, d->dmac_irq);
416 dpavlin 4
417 dpavlin 34 /*
418     * Register interrupts:
419     *
420     * 16 normal IRQs (emul[x].machine[x].cpu[x].ps2_intr.%i)
421     * 16 DMA IRQs (emul[x].machine[x].cpu[x].ps2_dmac.%i)
422     * 2 sbus IRQs (emul[x].machine[x].cpu[x].ps2_sbus.%i)
423     */
424     for (i=0; i<16; i++) {
425     snprintf(n, sizeof(n), "%s.ps2_intr.%i",
426     devinit->interrupt_path, i);
427     memset(&template, 0, sizeof(template));
428     template.line = i;
429     template.name = n;
430     template.extra = d;
431     template.interrupt_assert = ps2_intr_interrupt_assert;
432     template.interrupt_deassert = ps2_intr_interrupt_deassert;
433     interrupt_handler_register(&template);
434     }
435     for (i=0; i<16; i++) {
436     snprintf(n, sizeof(n), "%s.ps2_dmac.%i",
437     devinit->interrupt_path, i);
438     memset(&template, 0, sizeof(template));
439     template.line = i;
440     template.name = n;
441     template.extra = d;
442     template.interrupt_assert = ps2_dmac_interrupt_assert;
443     template.interrupt_deassert = ps2_dmac_interrupt_deassert;
444     interrupt_handler_register(&template);
445     }
446     for (i=0; i<2; i++) {
447     snprintf(n, sizeof(n), "%s.ps2_sbus.%i",
448     devinit->interrupt_path, i);
449     memset(&template, 0, sizeof(template));
450     template.line = i;
451     template.name = n;
452     template.extra = d;
453     template.interrupt_assert = ps2_sbus_interrupt_assert;
454     template.interrupt_deassert = ps2_sbus_interrupt_deassert;
455     interrupt_handler_register(&template);
456     }
457    
458     /* Connect to DMA channel 2 irq: */
459     snprintf(n, sizeof(n), "%s.ps2_dmac.2", devinit->interrupt_path);
460     INTERRUPT_CONNECT(n, d->dma_channel2_irq);
461    
462     /* Connect to SBUS interrupt, at ps2 interrupt 1: */
463     snprintf(n, sizeof(n), "%s.ps2_intr.1", devinit->interrupt_path);
464     INTERRUPT_CONNECT(n, d->sbus_irq);
465    
466     /* Connect to the timers' interrupts: */
467     for (i=0; i<N_PS2_TIMERS; i++) {
468     /* PS2 irq 9 is timer0, etc. */
469     snprintf(n, sizeof(n), "%s.ps2_intr.%i",
470     devinit->interrupt_path, 9 + i);
471     INTERRUPT_CONNECT(n, d->timer_irq[i]);
472     }
473    
474     memory_device_register(devinit->machine->memory, "ps2", devinit->addr,
475     DEV_PS2_LENGTH, dev_ps2_access, d, DM_DEFAULT, NULL);
476     machine_add_tickfunction(devinit->machine,
477     dev_ps2_tick, d, TICK_STEPS_SHIFT, 0.0);
478    
479     return 1;
480 dpavlin 4 }
481    
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