25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: dev_pccmos.c,v 1.3 2005/05/20 08:59:58 debug Exp $ |
* $Id: dev_pccmos.c,v 1.15 2005/11/21 22:27:18 debug Exp $ |
29 |
* |
* |
30 |
* PC CMOS/RTC device. |
* PC CMOS/RTC device. |
31 |
* |
* |
32 |
* This is mostly bogus. |
* The main point of this device is to be a "PC style wrapper" for accessing |
33 |
|
* the MC146818 (the RTC). In most other respects, this device is bogus, and |
34 |
|
* just acts as a 256-byte RAM device. |
35 |
*/ |
*/ |
36 |
|
|
37 |
#include <stdio.h> |
#include <stdio.h> |
65 |
{ |
{ |
66 |
struct pccmos_data *d = (struct pccmos_data *) extra; |
struct pccmos_data *d = (struct pccmos_data *) extra; |
67 |
uint64_t idata = 0, odata = 0; |
uint64_t idata = 0, odata = 0; |
68 |
|
unsigned char b = 0; |
69 |
|
int r = 1; |
70 |
|
|
71 |
idata = memory_readmax64(cpu, data, len); |
if (writeflag == MEM_WRITE) |
72 |
|
b = idata = memory_readmax64(cpu, data, len); |
73 |
|
|
74 |
switch (relative_addr) { |
/* |
75 |
case 0: if (writeflag == MEM_WRITE) { |
* Accesses to CMOS register 0 .. 0xd are rerouted to the |
76 |
|
* RTC; all other access are treated as CMOS RAM read/writes. |
77 |
|
*/ |
78 |
|
|
79 |
|
if ((relative_addr & 1) == 0) { |
80 |
|
if (writeflag == MEM_WRITE) { |
81 |
d->select = idata; |
d->select = idata; |
82 |
if (idata <= 0x0d) |
if (idata <= 0x0d) { |
83 |
cpu->memory_rw(cpu, cpu->mem, |
r = cpu->memory_rw(cpu, cpu->mem, |
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PCCMOS_MC146818_FAKE_ADDR, data, 1, |
PCCMOS_MC146818_FAKE_ADDR, &b, 1, |
85 |
MEM_WRITE, PHYSICAL); |
MEM_WRITE, PHYSICAL); |
86 |
|
} |
87 |
} else |
} else |
88 |
odata = d->select; |
odata = d->select; |
89 |
break; |
} else { |
90 |
case 1: if (d->select <= 0x0d) { |
if (d->select <= 0x0d) { |
91 |
if (writeflag == MEM_WRITE) |
if (writeflag == MEM_WRITE) { |
92 |
cpu->memory_rw(cpu, cpu->mem, |
r = cpu->memory_rw(cpu, cpu->mem, |
93 |
PCCMOS_MC146818_FAKE_ADDR + 1, data, 1, |
PCCMOS_MC146818_FAKE_ADDR + 1, &b, 1, |
94 |
MEM_WRITE, PHYSICAL); |
MEM_WRITE, PHYSICAL); |
95 |
else |
} else { |
96 |
cpu->memory_rw(cpu, cpu->mem, |
r = cpu->memory_rw(cpu, cpu->mem, |
97 |
PCCMOS_MC146818_FAKE_ADDR + 1, data, 1, |
PCCMOS_MC146818_FAKE_ADDR + 1, &b, 1, |
98 |
MEM_READ, PHYSICAL); |
MEM_READ, PHYSICAL); |
99 |
return 1; |
odata = b; |
100 |
|
} |
101 |
} else { |
} else { |
102 |
if (writeflag == MEM_WRITE) |
if (writeflag == MEM_WRITE) |
103 |
d->ram[d->select] = idata; |
d->ram[d->select] = idata; |
104 |
else |
else |
105 |
odata = d->ram[d->select]; |
odata = d->ram[d->select]; |
106 |
} |
} |
|
break; |
|
|
default: |
|
|
if (writeflag == MEM_WRITE) { |
|
|
fatal("[ pccmos: unimplemented write to address 0x%x" |
|
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" data=0x%02x ]\n", (int)relative_addr, (int)idata); |
|
|
} else { |
|
|
fatal("[ pccmos: unimplemented read from address 0x%x " |
|
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"]\n", (int)relative_addr); |
|
|
} |
|
107 |
} |
} |
108 |
|
|
109 |
|
if (r == 0) |
110 |
|
fatal("[ pccmos: memory_rw() error! ]\n"); |
111 |
|
|
112 |
if (writeflag == MEM_READ) |
if (writeflag == MEM_READ) |
113 |
memory_writemax64(cpu, data, len, odata); |
memory_writemax64(cpu, data, len, odata); |
114 |
|
|
122 |
int devinit_pccmos(struct devinit *devinit) |
int devinit_pccmos(struct devinit *devinit) |
123 |
{ |
{ |
124 |
struct pccmos_data *d = malloc(sizeof(struct pccmos_data)); |
struct pccmos_data *d = malloc(sizeof(struct pccmos_data)); |
125 |
|
int irq_nr, type = MC146818_PC_CMOS, len = DEV_PCCMOS_LENGTH; |
126 |
|
|
127 |
if (d == NULL) { |
if (d == NULL) { |
128 |
fprintf(stderr, "out of memory\n"); |
fprintf(stderr, "out of memory\n"); |
130 |
} |
} |
131 |
memset(d, 0, sizeof(struct pccmos_data)); |
memset(d, 0, sizeof(struct pccmos_data)); |
132 |
|
|
133 |
|
/* |
134 |
|
* Different machines use different IRQ schemes. |
135 |
|
*/ |
136 |
|
switch (devinit->machine->machine_type) { |
137 |
|
case MACHINE_CATS: |
138 |
|
case MACHINE_NETWINDER: |
139 |
|
irq_nr = 32 + 8; |
140 |
|
type = MC146818_CATS; |
141 |
|
d->ram[0x48] = 20; /* century */ |
142 |
|
len = DEV_PCCMOS_LENGTH * 2; |
143 |
|
break; |
144 |
|
case MACHINE_ALGOR: |
145 |
|
irq_nr = 8 + 8; |
146 |
|
type = MC146818_ALGOR; |
147 |
|
break; |
148 |
|
case MACHINE_EVBMIPS: |
149 |
|
/* Malta etc. */ |
150 |
|
irq_nr = 8 + 8; |
151 |
|
type = MC146818_ALGOR; |
152 |
|
break; |
153 |
|
case MACHINE_X86: |
154 |
|
irq_nr = 16; /* "No" irq */ |
155 |
|
break; |
156 |
|
case MACHINE_BEBOX: |
157 |
|
case MACHINE_PREP: |
158 |
|
irq_nr = 32 + 8; |
159 |
|
break; |
160 |
|
default:fatal("devinit_pccmos(): unimplemented machine type" |
161 |
|
" %i\n", devinit->machine->machine_type); |
162 |
|
exit(1); |
163 |
|
} |
164 |
|
|
165 |
memory_device_register(devinit->machine->memory, devinit->name, |
memory_device_register(devinit->machine->memory, devinit->name, |
166 |
devinit->addr, DEV_PCCMOS_LENGTH, dev_pccmos_access, (void *)d, |
devinit->addr, len, dev_pccmos_access, (void *)d, |
167 |
MEM_DEFAULT, NULL); |
DM_DEFAULT, NULL); |
168 |
|
|
169 |
dev_mc146818_init(devinit->machine, devinit->machine->memory, |
dev_mc146818_init(devinit->machine, devinit->machine->memory, |
170 |
PCCMOS_MC146818_FAKE_ADDR, 16 /* NOTE/TODO: No irq */, |
PCCMOS_MC146818_FAKE_ADDR, irq_nr, type, 1); |
|
MC146818_PC_CMOS, 1); |
|
171 |
|
|
172 |
return 1; |
return 1; |
173 |
} |
} |