25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: dev_pccmos.c,v 1.4 2005/10/04 04:11:14 debug Exp $ |
* $Id: dev_pccmos.c,v 1.8 2005/10/26 14:37:04 debug Exp $ |
29 |
* |
* |
30 |
* PC CMOS/RTC device. |
* PC CMOS/RTC device. |
31 |
* |
* |
65 |
{ |
{ |
66 |
struct pccmos_data *d = (struct pccmos_data *) extra; |
struct pccmos_data *d = (struct pccmos_data *) extra; |
67 |
uint64_t idata = 0, odata = 0; |
uint64_t idata = 0, odata = 0; |
68 |
unsigned char b; |
unsigned char b = 0; |
69 |
|
|
70 |
b = idata = memory_readmax64(cpu, data, len); |
if (writeflag == MEM_WRITE) |
71 |
|
b = idata = memory_readmax64(cpu, data, len); |
72 |
|
|
73 |
/* |
/* |
74 |
* Accesses to CMOS register 0 .. 0xd are rerouted to the |
* Accesses to CMOS register 0 .. 0xd are rerouted to the |
75 |
* RTC; all other access are treated as CMOS RAM read/writes. |
* RTC; all other access are treated as CMOS RAM read/writes. |
76 |
*/ |
*/ |
77 |
|
|
78 |
switch (relative_addr) { |
if ((relative_addr & 1) == 0) { |
79 |
case 0: if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
80 |
d->select = idata; |
d->select = idata; |
81 |
if (idata <= 0x0d) { |
if (idata <= 0x0d) { |
82 |
cpu->memory_rw(cpu, cpu->mem, |
cpu->memory_rw(cpu, cpu->mem, |
85 |
} |
} |
86 |
} else |
} else |
87 |
odata = d->select; |
odata = d->select; |
88 |
break; |
} else { |
89 |
case 1: if (d->select <= 0x0d) { |
if (d->select <= 0x0d) { |
90 |
if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
91 |
cpu->memory_rw(cpu, cpu->mem, |
cpu->memory_rw(cpu, cpu->mem, |
92 |
PCCMOS_MC146818_FAKE_ADDR + 1, &b, 1, |
PCCMOS_MC146818_FAKE_ADDR + 1, &b, 1, |
103 |
else |
else |
104 |
odata = d->ram[d->select]; |
odata = d->ram[d->select]; |
105 |
} |
} |
|
break; |
|
|
default: |
|
|
if (writeflag == MEM_WRITE) { |
|
|
fatal("[ pccmos: unimplemented write to address 0x%x" |
|
|
" data=0x%02x ]\n", (int)relative_addr, (int)idata); |
|
|
} else { |
|
|
fatal("[ pccmos: unimplemented read from address 0x%x " |
|
|
"]\n", (int)relative_addr); |
|
|
} |
|
106 |
} |
} |
107 |
|
|
108 |
if (writeflag == MEM_READ) |
if (writeflag == MEM_READ) |
118 |
int devinit_pccmos(struct devinit *devinit) |
int devinit_pccmos(struct devinit *devinit) |
119 |
{ |
{ |
120 |
struct pccmos_data *d = malloc(sizeof(struct pccmos_data)); |
struct pccmos_data *d = malloc(sizeof(struct pccmos_data)); |
121 |
int irq_nr; |
int irq_nr, type = MC146818_PC_CMOS, len = DEV_PCCMOS_LENGTH; |
122 |
|
|
123 |
if (d == NULL) { |
if (d == NULL) { |
124 |
fprintf(stderr, "out of memory\n"); |
fprintf(stderr, "out of memory\n"); |
126 |
} |
} |
127 |
memset(d, 0, sizeof(struct pccmos_data)); |
memset(d, 0, sizeof(struct pccmos_data)); |
128 |
|
|
|
memory_device_register(devinit->machine->memory, devinit->name, |
|
|
devinit->addr, DEV_PCCMOS_LENGTH, dev_pccmos_access, (void *)d, |
|
|
MEM_DEFAULT, NULL); |
|
|
|
|
129 |
/* |
/* |
130 |
* Different machines use different IRQ schemes. |
* Different machines use different IRQ schemes. |
131 |
*/ |
*/ |
132 |
switch (devinit->machine->machine_type) { |
switch (devinit->machine->machine_type) { |
133 |
case MACHINE_CATS: |
case MACHINE_CATS: |
134 |
irq_nr = 32 + 8; |
irq_nr = 32 + 8; |
135 |
|
type = MC146818_CATS; |
136 |
|
d->ram[0x48] = 20; /* century */ |
137 |
|
len = DEV_PCCMOS_LENGTH * 2; |
138 |
break; |
break; |
139 |
case MACHINE_X86: |
case MACHINE_X86: |
140 |
irq_nr = 16; /* "No" irq */ |
irq_nr = 16; /* "No" irq */ |
144 |
exit(1); |
exit(1); |
145 |
} |
} |
146 |
|
|
147 |
|
memory_device_register(devinit->machine->memory, devinit->name, |
148 |
|
devinit->addr, len, dev_pccmos_access, (void *)d, |
149 |
|
MEM_DEFAULT, NULL); |
150 |
|
|
151 |
dev_mc146818_init(devinit->machine, devinit->machine->memory, |
dev_mc146818_init(devinit->machine, devinit->machine->memory, |
152 |
PCCMOS_MC146818_FAKE_ADDR, irq_nr, MC146818_PC_CMOS, 1); |
PCCMOS_MC146818_FAKE_ADDR, irq_nr, type, 1); |
153 |
|
|
154 |
return 1; |
return 1; |
155 |
} |
} |