1 |
/* |
/* |
2 |
* Copyright (C) 2005 Anders Gavare. All rights reserved. |
* Copyright (C) 2005-2007 Anders Gavare. All rights reserved. |
3 |
* |
* |
4 |
* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
5 |
* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: dev_pccmos.c,v 1.7 2005/10/09 22:21:31 debug Exp $ |
* $Id: dev_pccmos.c,v 1.31 2007/06/15 19:57:33 debug Exp $ |
29 |
* |
* |
30 |
* PC CMOS/RTC device. |
* COMMENT: PC CMOS/RTC device (ISA ports 0x70 and 0x71) |
31 |
* |
* |
32 |
* The main point of this device is to be a "PC style wrapper" for accessing |
* The main point of this device is to be a "PC style wrapper" for accessing |
33 |
* the MC146818 (the RTC). In most other respects, this device is bogus, and |
* the MC146818 (the RTC). In most other respects, this device is bogus, and |
56 |
}; |
}; |
57 |
|
|
58 |
|
|
59 |
/* |
DEVICE_ACCESS(pccmos) |
|
* dev_pccmos_access(): |
|
|
*/ |
|
|
int dev_pccmos_access(struct cpu *cpu, struct memory *mem, |
|
|
uint64_t relative_addr, unsigned char *data, size_t len, |
|
|
int writeflag, void *extra) |
|
60 |
{ |
{ |
61 |
struct pccmos_data *d = (struct pccmos_data *) extra; |
struct pccmos_data *d = extra; |
62 |
uint64_t idata = 0, odata = 0; |
uint64_t idata = 0, odata = 0; |
63 |
unsigned char b; |
unsigned char b = 0; |
64 |
|
int r = 1; |
65 |
|
|
66 |
b = idata = memory_readmax64(cpu, data, len); |
if (writeflag == MEM_WRITE) |
67 |
|
b = idata = memory_readmax64(cpu, data, len); |
68 |
|
|
69 |
/* |
/* |
70 |
* Accesses to CMOS register 0 .. 0xd are rerouted to the |
* Accesses to CMOS register 0 .. 0xd are rerouted to the |
75 |
if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
76 |
d->select = idata; |
d->select = idata; |
77 |
if (idata <= 0x0d) { |
if (idata <= 0x0d) { |
78 |
cpu->memory_rw(cpu, cpu->mem, |
r = cpu->memory_rw(cpu, cpu->mem, |
79 |
PCCMOS_MC146818_FAKE_ADDR, &b, 1, |
PCCMOS_MC146818_FAKE_ADDR, &b, 1, |
80 |
MEM_WRITE, PHYSICAL); |
MEM_WRITE, PHYSICAL); |
81 |
} |
} |
84 |
} else { |
} else { |
85 |
if (d->select <= 0x0d) { |
if (d->select <= 0x0d) { |
86 |
if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
87 |
cpu->memory_rw(cpu, cpu->mem, |
r = cpu->memory_rw(cpu, cpu->mem, |
88 |
PCCMOS_MC146818_FAKE_ADDR + 1, &b, 1, |
PCCMOS_MC146818_FAKE_ADDR + 1, &b, 1, |
89 |
MEM_WRITE, PHYSICAL); |
MEM_WRITE, PHYSICAL); |
90 |
} else { |
} else { |
91 |
cpu->memory_rw(cpu, cpu->mem, |
r = cpu->memory_rw(cpu, cpu->mem, |
92 |
PCCMOS_MC146818_FAKE_ADDR + 1, &b, 1, |
PCCMOS_MC146818_FAKE_ADDR + 1, &b, 1, |
93 |
MEM_READ, PHYSICAL); |
MEM_READ, PHYSICAL); |
94 |
odata = b; |
odata = b; |
101 |
} |
} |
102 |
} |
} |
103 |
|
|
104 |
|
if (r == 0) |
105 |
|
fatal("[ pccmos: memory_rw() error! ]\n"); |
106 |
|
|
107 |
if (writeflag == MEM_READ) |
if (writeflag == MEM_READ) |
108 |
memory_writemax64(cpu, data, len, odata); |
memory_writemax64(cpu, data, len, odata); |
109 |
|
|
111 |
} |
} |
112 |
|
|
113 |
|
|
114 |
/* |
DEVINIT(pccmos) |
|
* devinit_pccmos(): |
|
|
*/ |
|
|
int devinit_pccmos(struct devinit *devinit) |
|
115 |
{ |
{ |
116 |
struct pccmos_data *d = malloc(sizeof(struct pccmos_data)); |
int type = MC146818_PC_CMOS, len = DEV_PCCMOS_LENGTH; |
117 |
int irq_nr, type = MC146818_PC_CMOS, len = DEV_PCCMOS_LENGTH; |
struct pccmos_data *d; |
118 |
|
|
119 |
if (d == NULL) { |
CHECK_ALLOCATION(d = malloc(sizeof(struct pccmos_data))); |
|
fprintf(stderr, "out of memory\n"); |
|
|
exit(1); |
|
|
} |
|
120 |
memset(d, 0, sizeof(struct pccmos_data)); |
memset(d, 0, sizeof(struct pccmos_data)); |
121 |
|
|
|
/* |
|
|
* Different machines use different IRQ schemes. |
|
|
*/ |
|
122 |
switch (devinit->machine->machine_type) { |
switch (devinit->machine->machine_type) { |
123 |
case MACHINE_CATS: |
case MACHINE_CATS: |
124 |
irq_nr = 32 + 8; |
case MACHINE_NETWINDER: |
125 |
type = MC146818_CATS; |
type = MC146818_CATS; |
126 |
d->ram[0x48] = 20; /* century */ |
d->ram[0x48] = 20; /* century */ |
127 |
len = DEV_PCCMOS_LENGTH * 2; |
len = DEV_PCCMOS_LENGTH * 2; |
128 |
break; |
break; |
129 |
case MACHINE_X86: |
case MACHINE_ALGOR: |
130 |
irq_nr = 16; /* "No" irq */ |
type = MC146818_ALGOR; |
131 |
|
break; |
132 |
|
case MACHINE_ARC: |
133 |
|
fatal("\nARC pccmos: TODO\n\n"); |
134 |
|
type = MC146818_ALGOR; |
135 |
|
break; |
136 |
|
case MACHINE_EVBMIPS: |
137 |
|
/* Malta etc. */ |
138 |
|
type = MC146818_ALGOR; |
139 |
|
break; |
140 |
|
case MACHINE_QEMU_MIPS: |
141 |
|
case MACHINE_COBALT: |
142 |
|
case MACHINE_BEBOX: |
143 |
|
case MACHINE_PREP: |
144 |
|
case MACHINE_MVMEPPC: |
145 |
|
case MACHINE_ALPHA: |
146 |
break; |
break; |
147 |
default:fatal("devinit_pccmos(): unimplemented machine type" |
default:fatal("devinit_pccmos(): unimplemented machine type" |
148 |
" %i\n", devinit->machine->machine_type); |
" %i\n", devinit->machine->machine_type); |
151 |
|
|
152 |
memory_device_register(devinit->machine->memory, devinit->name, |
memory_device_register(devinit->machine->memory, devinit->name, |
153 |
devinit->addr, len, dev_pccmos_access, (void *)d, |
devinit->addr, len, dev_pccmos_access, (void *)d, |
154 |
MEM_DEFAULT, NULL); |
DM_DEFAULT, NULL); |
155 |
|
|
156 |
dev_mc146818_init(devinit->machine, devinit->machine->memory, |
dev_mc146818_init(devinit->machine, devinit->machine->memory, |
157 |
PCCMOS_MC146818_FAKE_ADDR, irq_nr, type, 1); |
PCCMOS_MC146818_FAKE_ADDR, devinit->interrupt_path, type, 1); |
158 |
|
|
159 |
return 1; |
return 1; |
160 |
} |
} |