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/* |
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* Copyright (C) 2005-2007 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* $Id: dev_openpic.c,v 1.14 2007/09/11 21:42:52 debug Exp $ |
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* |
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* COMMENT: OpenPIC Interrupt controller (used by sandpoint ppc) |
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* based on dev_gc.c |
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*/ |
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|
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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|
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#include "cpu.h" |
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#include "device.h" |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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|
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|
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#define DEV_OPENPIC_LENGTH 0x40000 |
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|
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struct openpic_data { |
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struct interrupt cpu_irq; |
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|
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uint32_t status_hi; |
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uint32_t status_lo; |
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uint32_t enable_hi; |
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uint32_t enable_lo; |
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}; |
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|
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|
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void openpic_hi_interrupt_assert(struct interrupt *interrupt) |
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{ |
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struct openpic_data *d = interrupt->extra; |
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d->status_hi |= interrupt->line; |
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if (d->status_lo & d->enable_lo || d->status_hi & d->enable_hi) |
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INTERRUPT_ASSERT(d->cpu_irq); |
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} |
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void openpic_hi_interrupt_deassert(struct interrupt *interrupt) |
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{ |
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struct openpic_data *d = interrupt->extra; |
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d->status_hi &= ~interrupt->line; |
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if (!(d->status_lo & d->enable_lo || d->status_hi & d->enable_hi)) |
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INTERRUPT_DEASSERT(d->cpu_irq); |
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} |
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void openpic_lo_interrupt_assert(struct interrupt *interrupt) |
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{ |
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struct openpic_data *d = interrupt->extra; |
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d->status_lo |= interrupt->line; |
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if (d->status_lo & d->enable_lo || d->status_hi & d->enable_hi) |
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INTERRUPT_ASSERT(d->cpu_irq); |
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} |
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void openpic_lo_interrupt_deassert(struct interrupt *interrupt) |
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{ |
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struct openpic_data *d = interrupt->extra; |
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d->status_lo &= ~interrupt->line; |
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if (!(d->status_lo & d->enable_lo || d->status_hi & d->enable_hi)) |
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INTERRUPT_DEASSERT(d->cpu_irq); |
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} |
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|
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#define OPENPIC_MASK 0x80000000 |
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#define OPENPIC_ACTIVITY 0x40000000 /* Read Only */ |
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#define OPENPIC_PRIORITY_MASK 0x000f0000 |
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#define OPENPIC_PRIORITY_SHIFT 16 |
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#define OPENPIC_VECTOR_MASK 0x000000ff |
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|
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#define OPENPIC_VEC_TIMER 64 /* and up */ |
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#define OPENPIC_VEC_IPI 72 /* and up */ |
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#define OPENPIC_VEC_SPURIOUS 127 |
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|
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#define OPENPIC_NUM_TIMERS 4 |
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#define OPENPIC_NUM_IPI 4 |
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#define OPENPIC_NUM_PRI 16 |
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#define OPENPIC_NUM_VECTORS 256 |
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|
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DEVICE_ACCESS(openpic) |
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{ |
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// struct openpic_data *d = extra; |
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uint64_t idata = 0, odata = 0, decoded = 0; |
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|
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if (writeflag == MEM_WRITE) { |
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idata = memory_readmax64(cpu, data, len); |
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decoded = |
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( idata & 0x000000ff ) << 24 | |
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( idata & 0x0000ff00 ) << 8 | |
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( idata & 0x00ff0000 ) >> 8 | |
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( idata & 0xff000000 ) >> 24 ; |
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|
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uint64_t priority,vector, active; |
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priority = ( decoded & OPENPIC_PRIORITY_MASK ) >> OPENPIC_PRIORITY_SHIFT; |
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vector = ( decoded & OPENPIC_VECTOR_MASK ); |
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active = ( decoded & OPENPIC_ACTIVITY ); |
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|
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debug("[ openpic: WRITE %05x | %08x => %08x | priority: %x vector: 0x%02x %d active: %x ]\n", |
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(int)relative_addr, (int)idata, (int)decoded, (int)priority, (int)vector, (int)vector, (int)active ); |
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} |
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|
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switch (relative_addr) { |
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|
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case 0x00: |
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if (writeflag == MEM_READ) { |
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// version 1.2 |
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odata = 0x02000000; |
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fatal("[ openpic: read from " |
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"offset 0x%x (OpenPIC version) = %x]\n", (int) |
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relative_addr, (int)odata); |
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} |
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fatal("[ openpic: unimplemented write to " |
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"offset 0x%x: data=0x%x (OpenPIC version) ]\n", (int) |
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relative_addr, (int)idata); |
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break; |
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|
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#if 0 |
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#define INT_STATE_REG_H (interrupt_reg + 0x00) |
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#define INT_ENABLE_REG_H (interrupt_reg + 0x04) |
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#define INT_CLEAR_REG_H (interrupt_reg + 0x08) |
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#define INT_LEVEL_REG_H (interrupt_reg + 0x0c) |
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#define INT_STATE_REG_L (interrupt_reg + 0x10) |
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#define INT_ENABLE_REG_L (interrupt_reg + 0x14) |
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#define INT_CLEAR_REG_L (interrupt_reg + 0x18) |
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#define INT_LEVEL_REG_L (interrupt_reg + 0x1c) |
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|
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case 0x10: |
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if (writeflag == MEM_READ) |
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odata = d->status_hi & d->enable_hi; |
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break; |
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|
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case 0x14: |
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if (writeflag == MEM_READ) |
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odata = d->enable_hi; |
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else { |
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int old_assert = (d->status_lo & d->enable_lo |
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|| d->status_hi & d->enable_hi); |
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int new_assert; |
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d->enable_hi = idata; |
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|
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new_assert = (d->status_lo & d->enable_lo || |
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d->status_hi & d->enable_hi); |
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|
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if (old_assert && !new_assert) |
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INTERRUPT_DEASSERT(d->cpu_irq); |
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else if (!old_assert && new_assert) |
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INTERRUPT_ASSERT(d->cpu_irq); |
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} |
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break; |
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|
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case 0x18: |
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if (writeflag == MEM_WRITE) { |
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int old_assert = (d->status_lo & d->enable_lo |
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|| d->status_hi & d->enable_hi); |
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int new_assert; |
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d->status_hi &= ~idata; |
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|
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new_assert = (d->status_lo & d->enable_lo || |
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d->status_hi & d->enable_hi); |
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|
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if (old_assert && !new_assert) |
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INTERRUPT_DEASSERT(d->cpu_irq); |
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else if (!old_assert && new_assert) |
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INTERRUPT_ASSERT(d->cpu_irq); |
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} |
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break; |
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|
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case 0x20: |
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if (writeflag == MEM_READ) |
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odata = d->status_lo & d->enable_lo; |
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break; |
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|
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case 0x24: |
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if (writeflag == MEM_READ) |
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odata = d->enable_lo; |
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else { |
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int old_assert = (d->status_lo & d->enable_lo |
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|| d->status_hi & d->enable_hi); |
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int new_assert; |
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d->enable_lo = idata; |
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|
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new_assert = (d->status_lo & d->enable_lo || |
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d->status_hi & d->enable_hi); |
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|
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if (old_assert && !new_assert) |
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INTERRUPT_DEASSERT(d->cpu_irq); |
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else if (!old_assert && new_assert) |
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INTERRUPT_ASSERT(d->cpu_irq); |
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} |
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break; |
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|
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case 0x28: |
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if (writeflag == MEM_WRITE) { |
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int old_assert = (d->status_lo & d->enable_lo |
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|| d->status_hi & d->enable_hi); |
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int new_assert; |
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d->status_lo &= ~idata; |
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|
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new_assert = (d->status_lo & d->enable_lo || |
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d->status_hi & d->enable_hi); |
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|
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if (old_assert && !new_assert) |
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INTERRUPT_DEASSERT(d->cpu_irq); |
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else if (!old_assert && new_assert) |
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INTERRUPT_ASSERT(d->cpu_irq); |
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} |
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break; |
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|
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case 0x1c: |
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case 0x2c: |
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/* Avoid a debug message. */ |
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break; |
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#endif |
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default:if (writeflag == MEM_WRITE) { |
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fatal("[ openpic: unimplemented write to " |
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"offset 0x%x: data=0x%x ]\n", (int) |
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relative_addr, (int)idata); |
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} else { |
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fatal("[ openpic: unimplemented read from " |
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"offset 0x%x ]\n", (int)relative_addr); |
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} |
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} |
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|
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if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len, odata); |
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|
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return 1; |
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} |
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|
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|
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DEVINIT(openpic) |
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{ |
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struct openpic_data *d; |
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int i; |
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|
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CHECK_ALLOCATION(d = malloc(sizeof(struct openpic_data))); |
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memset(d, 0, sizeof(struct openpic_data)); |
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|
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/* Connect to the CPU interrupt pin: */ |
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INTERRUPT_CONNECT(devinit->interrupt_path, d->cpu_irq); |
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|
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/* |
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* Register the 126 OpenPIC interrupts |
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*/ |
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for (i=0; i<126; i++) { |
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struct interrupt template; |
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char n[300]; |
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snprintf(n, sizeof(n), "%s.openpic.%i", |
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devinit->interrupt_path, i); |
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memset(&template, 0, sizeof(template)); |
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template.line = 1 << i; |
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template.name = n; |
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template.extra = d; |
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template.interrupt_assert = openpic_lo_interrupt_assert; |
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template.interrupt_deassert = openpic_lo_interrupt_deassert; |
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interrupt_handler_register(&template); |
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} |
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|
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memory_device_register(devinit->machine->memory, "openpic", |
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devinit->addr, DEV_OPENPIC_LENGTH, dev_openpic_access, d, DM_DEFAULT, NULL); |
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|
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return 1; |
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} |
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