/[gxemul]/trunk/src/devices/dev_openpic.c
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Contents of /trunk/src/devices/dev_openpic.c

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Revision 63 - (show annotations)
Sat Oct 13 15:05:59 2007 UTC (13 years, 8 months ago) by dpavlin
File MIME type: text/plain
File size: 7243 byte(s)
create OpenPIC
1 /*
2 * Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $Id: dev_openpic.c,v 1.14 2007/09/11 21:42:52 debug Exp $
28 *
29 * COMMENT: OpenPIC Interrupt controller (used by sandpoint ppc)
30 * based on dev_openpic.c
31 */
32
33 #include <stdio.h>
34 #include <stdlib.h>
35 #include <string.h>
36
37 #include "cpu.h"
38 #include "device.h"
39 #include "machine.h"
40 #include "memory.h"
41 #include "misc.h"
42
43
44 #define DEV_OPENPIC_LENGTH 0x40000
45
46 struct openpic_data {
47 struct interrupt cpu_irq;
48
49 uint32_t status_hi;
50 uint32_t status_lo;
51 uint32_t enable_hi;
52 uint32_t enable_lo;
53 };
54
55
56 void openpic_hi_interrupt_assert(struct interrupt *interrupt)
57 {
58 struct openpic_data *d = interrupt->extra;
59 d->status_hi |= interrupt->line;
60 if (d->status_lo & d->enable_lo || d->status_hi & d->enable_hi)
61 INTERRUPT_ASSERT(d->cpu_irq);
62 }
63 void openpic_hi_interrupt_deassert(struct interrupt *interrupt)
64 {
65 struct openpic_data *d = interrupt->extra;
66 d->status_hi &= ~interrupt->line;
67 if (!(d->status_lo & d->enable_lo || d->status_hi & d->enable_hi))
68 INTERRUPT_DEASSERT(d->cpu_irq);
69 }
70 void openpic_lo_interrupt_assert(struct interrupt *interrupt)
71 {
72 struct openpic_data *d = interrupt->extra;
73 d->status_lo |= interrupt->line;
74 if (d->status_lo & d->enable_lo || d->status_hi & d->enable_hi)
75 INTERRUPT_ASSERT(d->cpu_irq);
76 }
77 void openpic_lo_interrupt_deassert(struct interrupt *interrupt)
78 {
79 struct openpic_data *d = interrupt->extra;
80 d->status_lo &= ~interrupt->line;
81 if (!(d->status_lo & d->enable_lo || d->status_hi & d->enable_hi))
82 INTERRUPT_DEASSERT(d->cpu_irq);
83 }
84
85
86 DEVICE_ACCESS(openpic)
87 {
88 struct openpic_data *d = extra;
89 uint64_t idata = 0, odata = 0;
90
91 if (writeflag == MEM_WRITE)
92 idata = memory_readmax64(cpu, data, len);
93
94 switch (relative_addr) {
95
96 #if 0
97 #define INT_STATE_REG_H (interrupt_reg + 0x00)
98 #define INT_ENABLE_REG_H (interrupt_reg + 0x04)
99 #define INT_CLEAR_REG_H (interrupt_reg + 0x08)
100 #define INT_LEVEL_REG_H (interrupt_reg + 0x0c)
101 #define INT_STATE_REG_L (interrupt_reg + 0x10)
102 #define INT_ENABLE_REG_L (interrupt_reg + 0x14)
103 #define INT_CLEAR_REG_L (interrupt_reg + 0x18)
104 #define INT_LEVEL_REG_L (interrupt_reg + 0x1c)
105 #endif
106
107 case 0x10:
108 if (writeflag == MEM_READ)
109 odata = d->status_hi & d->enable_hi;
110 break;
111
112 case 0x14:
113 if (writeflag == MEM_READ)
114 odata = d->enable_hi;
115 else {
116 int old_assert = (d->status_lo & d->enable_lo
117 || d->status_hi & d->enable_hi);
118 int new_assert;
119 d->enable_hi = idata;
120
121 new_assert = (d->status_lo & d->enable_lo ||
122 d->status_hi & d->enable_hi);
123
124 if (old_assert && !new_assert)
125 INTERRUPT_DEASSERT(d->cpu_irq);
126 else if (!old_assert && new_assert)
127 INTERRUPT_ASSERT(d->cpu_irq);
128 }
129 break;
130
131 case 0x18:
132 if (writeflag == MEM_WRITE) {
133 int old_assert = (d->status_lo & d->enable_lo
134 || d->status_hi & d->enable_hi);
135 int new_assert;
136 d->status_hi &= ~idata;
137
138 new_assert = (d->status_lo & d->enable_lo ||
139 d->status_hi & d->enable_hi);
140
141 if (old_assert && !new_assert)
142 INTERRUPT_DEASSERT(d->cpu_irq);
143 else if (!old_assert && new_assert)
144 INTERRUPT_ASSERT(d->cpu_irq);
145 }
146 break;
147
148 case 0x20:
149 if (writeflag == MEM_READ)
150 odata = d->status_lo & d->enable_lo;
151 break;
152
153 case 0x24:
154 if (writeflag == MEM_READ)
155 odata = d->enable_lo;
156 else {
157 int old_assert = (d->status_lo & d->enable_lo
158 || d->status_hi & d->enable_hi);
159 int new_assert;
160 d->enable_lo = idata;
161
162 new_assert = (d->status_lo & d->enable_lo ||
163 d->status_hi & d->enable_hi);
164
165 if (old_assert && !new_assert)
166 INTERRUPT_DEASSERT(d->cpu_irq);
167 else if (!old_assert && new_assert)
168 INTERRUPT_ASSERT(d->cpu_irq);
169 }
170 break;
171
172 case 0x28:
173 if (writeflag == MEM_WRITE) {
174 int old_assert = (d->status_lo & d->enable_lo
175 || d->status_hi & d->enable_hi);
176 int new_assert;
177 d->status_lo &= ~idata;
178
179 new_assert = (d->status_lo & d->enable_lo ||
180 d->status_hi & d->enable_hi);
181
182 if (old_assert && !new_assert)
183 INTERRUPT_DEASSERT(d->cpu_irq);
184 else if (!old_assert && new_assert)
185 INTERRUPT_ASSERT(d->cpu_irq);
186 }
187 break;
188
189 case 0x1c:
190 case 0x2c:
191 /* Avoid a debug message. */
192 break;
193
194 default:if (writeflag == MEM_WRITE) {
195 fatal("[ openpic: unimplemented write to "
196 "offset 0x%x: data=0x%x ]\n", (int)
197 relative_addr, (int)idata);
198 } else {
199 fatal("[ openpic: unimplemented read from "
200 "offset 0x%x ]\n", (int)relative_addr);
201 }
202 }
203
204 if (writeflag == MEM_READ)
205 memory_writemax64(cpu, data, len, odata);
206
207 return 1;
208 }
209
210
211 DEVINIT(openpic)
212 {
213 struct openpic_data *d;
214 int i;
215
216 CHECK_ALLOCATION(d = malloc(sizeof(struct openpic_data)));
217 memset(d, 0, sizeof(struct openpic_data));
218
219 /* Connect to the CPU interrupt pin: */
220 INTERRUPT_CONNECT(devinit->interrupt_path, d->cpu_irq);
221
222 /*
223 * Register the 64 Grand Central interrupts (32 lo, 32 hi):
224 */
225 for (i=0; i<32; i++) {
226 struct interrupt template;
227 char n[300];
228 snprintf(n, sizeof(n), "%s.openpic.lo.%i",
229 devinit->interrupt_path, i);
230 memset(&template, 0, sizeof(template));
231 template.line = 1 << i;
232 template.name = n;
233 template.extra = d;
234 template.interrupt_assert = openpic_lo_interrupt_assert;
235 template.interrupt_deassert = openpic_lo_interrupt_deassert;
236 interrupt_handler_register(&template);
237
238 snprintf(n, sizeof(n), "%s.openpic.hi.%i",
239 devinit->interrupt_path, i);
240 memset(&template, 0, sizeof(template));
241 template.line = 1 << i;
242 template.name = n;
243 template.extra = d;
244 template.interrupt_assert = openpic_hi_interrupt_assert;
245 template.interrupt_deassert = openpic_hi_interrupt_deassert;
246 interrupt_handler_register(&template);
247 }
248
249 memory_device_register(devinit->machine->memory, "openpic",
250 devinit->addr, DEV_OPENPIC_LENGTH, dev_openpic_access, d, DM_DEFAULT, NULL);
251
252 return 1;
253 }
254

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