--- trunk/src/devices/dev_openpic.c	2007/10/13 15:43:48	64
+++ trunk/src/devices/dev_openpic.c	2007/10/14 13:46:39	67
@@ -82,17 +82,58 @@
 		INTERRUPT_DEASSERT(d->cpu_irq);
 }
 
+#define OPENPIC_MASK                            0x80000000
+#define OPENPIC_ACTIVITY                        0x40000000      /* Read Only */
+#define OPENPIC_PRIORITY_MASK                   0x000f0000
+#define OPENPIC_PRIORITY_SHIFT                  16
+#define OPENPIC_VECTOR_MASK                     0x000000ff
+
+#define OPENPIC_VEC_TIMER       64      /* and up */
+#define OPENPIC_VEC_IPI         72      /* and up */
+#define OPENPIC_VEC_SPURIOUS    127
+
+#define OPENPIC_NUM_TIMERS      4
+#define OPENPIC_NUM_IPI         4
+#define OPENPIC_NUM_PRI         16
+#define OPENPIC_NUM_VECTORS     256
 
 DEVICE_ACCESS(openpic)
 {
 //	struct openpic_data *d = extra;
-	uint64_t idata = 0, odata = 0;
+	uint64_t idata = 0, odata = 0, decoded = 0;
 
-	if (writeflag == MEM_WRITE)
+	if (writeflag == MEM_WRITE) {
 		idata = memory_readmax64(cpu, data, len);
+		decoded =
+			( idata & 0x000000ff ) << 24 |
+			( idata & 0x0000ff00 ) << 8  |
+			( idata & 0x00ff0000 ) >> 8  |
+			( idata & 0xff000000 ) >> 24 ;
+
+		uint64_t priority,vector, active;
+		priority = ( decoded & OPENPIC_PRIORITY_MASK ) >> OPENPIC_PRIORITY_SHIFT;
+		vector   = ( decoded & OPENPIC_VECTOR_MASK );
+		active	 = ( decoded & OPENPIC_ACTIVITY );
+
+		debug("[ openpic: WRITE %05x | %08x => %08x | priority: %x vector: 0x%02x %d active: %x ]\n",
+			(int)relative_addr, (int)idata, (int)decoded, (int)priority, (int)vector, (int)vector, (int)active );
+	}
 
 	switch (relative_addr) {
 
+	case 0x00:
+		if (writeflag == MEM_READ) {
+			// version 1.2
+			odata = 0x02000000;
+			fatal("[ openpic: read from "
+			    "offset 0x%x (OpenPIC version) = %x]\n", (int)
+			    relative_addr, (int)odata);
+		}
+		fatal("[ openpic: unimplemented write to "
+		    "offset 0x%x: data=0x%x (OpenPIC version) ]\n", (int)
+		    relative_addr, (int)idata);
+		break;
+
 #if 0
 #define INT_STATE_REG_H  (interrupt_reg + 0x00)
 #define INT_ENABLE_REG_H (interrupt_reg + 0x04)
@@ -102,9 +143,7 @@
 #define INT_ENABLE_REG_L (interrupt_reg + 0x14)
 #define INT_CLEAR_REG_L  (interrupt_reg + 0x18)
 #define INT_LEVEL_REG_L  (interrupt_reg + 0x1c)
-#endif
 
-#if 0
 	case 0x10:
 		if (writeflag == MEM_READ)
 			odata = d->status_hi & d->enable_hi;