82 |
INTERRUPT_DEASSERT(d->cpu_irq); |
INTERRUPT_DEASSERT(d->cpu_irq); |
83 |
} |
} |
84 |
|
|
85 |
|
/* |
86 |
|
* FIXME acitvity is never sat |
87 |
|
*/ |
88 |
|
|
89 |
#define OPENPIC_MASK 0x80000000 |
#define OPENPIC_MASK 0x80000000 |
90 |
#define OPENPIC_ACTIVITY 0x40000000 /* Read Only */ |
#define OPENPIC_ACTIVITY 0x40000000 /* Read Only */ |
91 |
#define OPENPIC_PRIORITY_MASK 0x000f0000 |
#define OPENPIC_PRIORITY_MASK 0x000f0000 |
104 |
DEVICE_ACCESS(openpic) |
DEVICE_ACCESS(openpic) |
105 |
{ |
{ |
106 |
// struct openpic_data *d = extra; |
// struct openpic_data *d = extra; |
107 |
uint64_t idata = 0, odata = 0, decoded = 0; |
uint64_t idata = 0, odata = 0; |
108 |
|
|
109 |
if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
110 |
idata = memory_readmax64(cpu, data, len); |
idata = memory_readmax64(cpu, data, len); |
111 |
decoded = |
// shuffle byte order |
112 |
|
idata = |
113 |
( idata & 0x000000ff ) << 24 | |
( idata & 0x000000ff ) << 24 | |
114 |
( idata & 0x0000ff00 ) << 8 | |
( idata & 0x0000ff00 ) << 8 | |
115 |
( idata & 0x00ff0000 ) >> 8 | |
( idata & 0x00ff0000 ) >> 8 | |
116 |
( idata & 0xff000000 ) >> 24 ; |
( idata & 0xff000000 ) >> 24 ; |
117 |
|
|
118 |
uint64_t priority,vector, active; |
uint64_t priority,vector, active; |
119 |
priority = ( decoded & OPENPIC_PRIORITY_MASK ) >> OPENPIC_PRIORITY_SHIFT; |
priority = ( idata & OPENPIC_PRIORITY_MASK ) >> OPENPIC_PRIORITY_SHIFT; |
120 |
vector = ( decoded & OPENPIC_VECTOR_MASK ); |
vector = ( idata & OPENPIC_VECTOR_MASK ); |
121 |
active = ( decoded & OPENPIC_ACTIVITY ); |
active = ( idata & OPENPIC_ACTIVITY ); |
122 |
|
|
123 |
debug("[ openpic: WRITE %05x | %08x => %08x | priority: %x vector: 0x%02x %d active: %x ]\n", |
debug("[ openpic: WRITE %05x | %08x | priority: %x vector: 0x%02x %d active: %x ]\n", |
124 |
(int)relative_addr, (int)idata, (int)decoded, (int)priority, (int)vector, (int)vector, (int)active ); |
(int)relative_addr, (int)idata, (int)priority, (int)vector, (int)vector, (int)active ); |
125 |
} |
} |
126 |
|
|
127 |
switch (relative_addr) { |
switch (relative_addr) { |
128 |
|
|
129 |
|
// version |
130 |
case 0x00: |
case 0x00: |
131 |
if (writeflag == MEM_READ) { |
if (writeflag == MEM_READ) { |
132 |
// version 1.2 |
// version 1.2 |
133 |
odata = 0x02000000; |
odata = 0x02000000; |
134 |
fatal("[ openpic: read from " |
fatal("[ openpic: read version " |
135 |
"offset 0x%x (OpenPIC version) = %x]\n", (int) |
"offset 0x%x = %x]\n", (int) |
136 |
relative_addr, (int)odata); |
relative_addr, (int)odata); |
137 |
} |
} |
138 |
fatal("[ openpic: unimplemented write to " |
fatal("[ openpic: unimplemented write to " |
140 |
relative_addr, (int)idata); |
relative_addr, (int)idata); |
141 |
break; |
break; |
142 |
|
|
143 |
|
// global timer frequency |
144 |
|
case 0xf0: |
145 |
|
if (writeflag == MEM_READ) { |
146 |
|
odata = 170 * 1000000; // MHz |
147 |
|
fatal("[ openpic: read global timer frequency " |
148 |
|
"offset 0x%x = %x]\n", (int) |
149 |
|
relative_addr, (int)odata); |
150 |
|
} |
151 |
|
fatal("[ openpic: unimplemented write to " |
152 |
|
"offset 0x%x: data=0x%x ]\n", (int) |
153 |
|
relative_addr, (int)idata); |
154 |
|
break; |
155 |
|
|
156 |
#if 0 |
#if 0 |
157 |
#define INT_STATE_REG_H (interrupt_reg + 0x00) |
#define INT_STATE_REG_H (interrupt_reg + 0x00) |
158 |
#define INT_ENABLE_REG_H (interrupt_reg + 0x04) |
#define INT_ENABLE_REG_H (interrupt_reg + 0x04) |
250 |
/* Avoid a debug message. */ |
/* Avoid a debug message. */ |
251 |
break; |
break; |
252 |
#endif |
#endif |
253 |
default:if (writeflag == MEM_WRITE) { |
default: |
254 |
|
if (writeflag == MEM_WRITE) { |
255 |
fatal("[ openpic: unimplemented write to " |
fatal("[ openpic: unimplemented write to " |
256 |
"offset 0x%x: data=0x%x ]\n", (int) |
"offset 0x%x idata = %x ]\n", |
257 |
relative_addr, (int)idata); |
(int)relative_addr, (int)idata |
258 |
|
); |
259 |
} else { |
} else { |
260 |
fatal("[ openpic: unimplemented read from " |
fatal("[ openpic: unimplemented read from " |
261 |
"offset 0x%x ]\n", (int)relative_addr); |
"offset 0x%x odata = %x ]\n", |
262 |
|
(int)relative_addr, (int)odata |
263 |
|
); |
264 |
} |
} |
265 |
} |
} |
266 |
|
|
267 |
if (writeflag == MEM_READ) |
if (writeflag == MEM_READ) { |
268 |
|
// shuffle byte order |
269 |
|
odata = |
270 |
|
( odata & 0x000000ff ) << 24 | |
271 |
|
( odata & 0x0000ff00 ) << 8 | |
272 |
|
( odata & 0x00ff0000 ) >> 8 | |
273 |
|
( odata & 0xff000000 ) >> 24 ; |
274 |
memory_writemax64(cpu, data, len, odata); |
memory_writemax64(cpu, data, len, odata); |
275 |
|
debug("[ openpic: READ %05x | %08x ]\n", |
276 |
|
(int)relative_addr, (int)odata |
277 |
|
); |
278 |
|
} |
279 |
|
|
280 |
return 1; |
return 1; |
281 |
} |
} |
307 |
template.interrupt_assert = openpic_lo_interrupt_assert; |
template.interrupt_assert = openpic_lo_interrupt_assert; |
308 |
template.interrupt_deassert = openpic_lo_interrupt_deassert; |
template.interrupt_deassert = openpic_lo_interrupt_deassert; |
309 |
interrupt_handler_register(&template); |
interrupt_handler_register(&template); |
310 |
|
debug("[ openpic: added interrupt %s ]\n", n); |
311 |
} |
} |
312 |
|
|
313 |
memory_device_register(devinit->machine->memory, "openpic", |
memory_device_register(devinit->machine->memory, "openpic", |