src/devices/dev_openpic.c

/*
 *  Copyright (C) 2005-2007  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *   
 *  $Id: dev_openpic.c,v 1.14 2007/09/11 21:42:52 debug Exp $
 *  
 *  COMMENT: OpenPIC Interrupt controller (used by sandpoint ppc)
 *  based on dev_gc.c
 */

#include <stdio.h>
#include <stdlib.h>
#include <string.h>

#include "cpu.h"
#include "device.h"
#include "machine.h"
#include "memory.h"
#include "misc.h"


#define DEV_OPENPIC_LENGTH              0x40000

struct openpic_data {
        struct interrupt cpu_irq;

        uint32_t        status_hi;
        uint32_t        status_lo;
        uint32_t        enable_hi;
        uint32_t        enable_lo;
};


void openpic_hi_interrupt_assert(struct interrupt *interrupt)
{
        struct openpic_data *d = interrupt->extra;
        d->status_hi |= interrupt->line;
        if (d->status_lo & d->enable_lo || d->status_hi & d->enable_hi)
                INTERRUPT_ASSERT(d->cpu_irq);
}
void openpic_hi_interrupt_deassert(struct interrupt *interrupt)
{
        struct openpic_data *d = interrupt->extra;
        d->status_hi &= ~interrupt->line;
        if (!(d->status_lo & d->enable_lo || d->status_hi & d->enable_hi))
                INTERRUPT_DEASSERT(d->cpu_irq);
}
void openpic_lo_interrupt_assert(struct interrupt *interrupt)
{
        struct openpic_data *d = interrupt->extra;
        d->status_lo |= interrupt->line;
        if (d->status_lo & d->enable_lo || d->status_hi & d->enable_hi)
                INTERRUPT_ASSERT(d->cpu_irq);
}
void openpic_lo_interrupt_deassert(struct interrupt *interrupt)
{
        struct openpic_data *d = interrupt->extra;
        d->status_lo &= ~interrupt->line;
        if (!(d->status_lo & d->enable_lo || d->status_hi & d->enable_hi))
                INTERRUPT_DEASSERT(d->cpu_irq);
}

/*
 * FIXME acitvity is never sat
 */

#define OPENPIC_MASK                            0x80000000
#define OPENPIC_ACTIVITY                        0x40000000      /* Read Only */
#define OPENPIC_PRIORITY_MASK                   0x000f0000
#define OPENPIC_PRIORITY_SHIFT                  16
#define OPENPIC_VECTOR_MASK                     0x000000ff

#define OPENPIC_VEC_TIMER       64      /* and up */
#define OPENPIC_VEC_IPI         72      /* and up */
#define OPENPIC_VEC_SPURIOUS    127

#define OPENPIC_NUM_TIMERS      4
#define OPENPIC_NUM_IPI         4
#define OPENPIC_NUM_PRI         16
#define OPENPIC_NUM_VECTORS     256

DEVICE_ACCESS(openpic)
{
//      struct openpic_data *d = extra;
        uint64_t idata = 0, odata = 0;

        if (writeflag == MEM_WRITE) {
                idata = memory_readmax64(cpu, data, len);
                // shuffle byte order
                idata =
                        ( idata & 0x000000ff ) << 24 |
                        ( idata & 0x0000ff00 ) << 8  |
                        ( idata & 0x00ff0000 ) >> 8  |
                        ( idata & 0xff000000 ) >> 24 ;

                uint64_t priority,vector, active;
                priority = ( idata & OPENPIC_PRIORITY_MASK ) >> OPENPIC_PRIORITY_SHIFT;
                vector   = ( idata & OPENPIC_VECTOR_MASK );
                active   = ( idata & OPENPIC_ACTIVITY );

                debug("[ openpic: WRITE %05x | %08x | priority: %x vector: 0x%02x %d active: %x ]\n",
                        (int)relative_addr, (int)idata, (int)priority, (int)vector, (int)vector, (int)active );
        }

        switch (relative_addr) {

        // version
        case 0x00:
                if (writeflag == MEM_READ) {
                        // version 1.2
                        odata = 0x02000000;
                        fatal("[ openpic: read version "
                            "offset 0x%x = %x]\n", (int)
                            relative_addr, (int)odata);
                }
                fatal("[ openpic: unimplemented write to "
                    "offset 0x%x: data=0x%x (OpenPIC version) ]\n", (int)
                    relative_addr, (int)idata);
                break;

        // global timer frequency
        case 0xf0:
                if (writeflag == MEM_READ) {
                        odata = 170 * 1000000;  // MHz
                        fatal("[ openpic: read global timer frequency "
                            "offset 0x%x = %x]\n", (int)
                            relative_addr, (int)odata);
                }
                fatal("[ openpic: unimplemented write to "
                    "offset 0x%x: data=0x%x ]\n", (int)
                    relative_addr, (int)idata);
                break;

#if 0
#define INT_STATE_REG_H  (interrupt_reg + 0x00)
#define INT_ENABLE_REG_H (interrupt_reg + 0x04)
#define INT_CLEAR_REG_H  (interrupt_reg + 0x08)
#define INT_LEVEL_REG_H  (interrupt_reg + 0x0c)
#define INT_STATE_REG_L  (interrupt_reg + 0x10)
#define INT_ENABLE_REG_L (interrupt_reg + 0x14)
#define INT_CLEAR_REG_L  (interrupt_reg + 0x18)
#define INT_LEVEL_REG_L  (interrupt_reg + 0x1c)

        case 0x10:
                if (writeflag == MEM_READ)
                        odata = d->status_hi & d->enable_hi;
                break;

        case 0x14:
                if (writeflag == MEM_READ)
                        odata = d->enable_hi;
                else {
                        int old_assert = (d->status_lo & d->enable_lo
                            || d->status_hi & d->enable_hi);
                        int new_assert;
                        d->enable_hi = idata;

                        new_assert = (d->status_lo & d->enable_lo ||
                            d->status_hi & d->enable_hi);

                        if (old_assert && !new_assert)
                                INTERRUPT_DEASSERT(d->cpu_irq);
                        else if (!old_assert && new_assert)
                                INTERRUPT_ASSERT(d->cpu_irq);
                }
                break;

        case 0x18:
                if (writeflag == MEM_WRITE) {
                        int old_assert = (d->status_lo & d->enable_lo
                            || d->status_hi & d->enable_hi);
                        int new_assert;
                        d->status_hi &= ~idata;

                        new_assert = (d->status_lo & d->enable_lo ||
                            d->status_hi & d->enable_hi);

                        if (old_assert && !new_assert)
                                INTERRUPT_DEASSERT(d->cpu_irq);
                        else if (!old_assert && new_assert)
                                INTERRUPT_ASSERT(d->cpu_irq);
                }
                break;

        case 0x20:
                if (writeflag == MEM_READ)
                        odata = d->status_lo & d->enable_lo;
                break;

        case 0x24:
                if (writeflag == MEM_READ)
                        odata = d->enable_lo;
                else {
                        int old_assert = (d->status_lo & d->enable_lo
                            || d->status_hi & d->enable_hi);
                        int new_assert;
                        d->enable_lo = idata;

                        new_assert = (d->status_lo & d->enable_lo ||
                            d->status_hi & d->enable_hi);

                        if (old_assert && !new_assert)
                                INTERRUPT_DEASSERT(d->cpu_irq);
                        else if (!old_assert && new_assert)
                                INTERRUPT_ASSERT(d->cpu_irq);
                }
                break;

        case 0x28:
                if (writeflag == MEM_WRITE) {
                        int old_assert = (d->status_lo & d->enable_lo
                            || d->status_hi & d->enable_hi);
                        int new_assert;
                        d->status_lo &= ~idata;

                        new_assert = (d->status_lo & d->enable_lo ||
                            d->status_hi & d->enable_hi);

                        if (old_assert && !new_assert)
                                INTERRUPT_DEASSERT(d->cpu_irq);
                        else if (!old_assert && new_assert)
                                INTERRUPT_ASSERT(d->cpu_irq);
                }
                break;

        case 0x1c:
        case 0x2c:
                /*  Avoid a debug message.  */
                break;
#endif
        default:
                if (writeflag == MEM_WRITE) {
                        fatal("[ openpic: unimplemented write to "
                                "offset 0x%x idata = %x ]\n",
                                (int)relative_addr, (int)idata
                        );
                } else {
                        fatal("[ openpic: unimplemented read from "
                                "offset 0x%x odata = %x ]\n",
                                (int)relative_addr, (int)odata
                        );
                }
        }

        if (writeflag == MEM_READ) {
                // shuffle byte order
                odata =
                        ( odata & 0x000000ff ) << 24 |
                        ( odata & 0x0000ff00 ) << 8  |
                        ( odata & 0x00ff0000 ) >> 8  |
                        ( odata & 0xff000000 ) >> 24 ;
                memory_writemax64(cpu, data, len, odata);
                debug("[ openpic: READ %05x | %08x ]\n",
                        (int)relative_addr, (int)odata
                );
        }

        return 1;
}


DEVINIT(openpic)
{
        struct openpic_data *d;
        int i;

        CHECK_ALLOCATION(d = malloc(sizeof(struct openpic_data)));
        memset(d, 0, sizeof(struct openpic_data));

        /*  Connect to the CPU interrupt pin:  */
        INTERRUPT_CONNECT(devinit->interrupt_path, d->cpu_irq);

        /*
         *  Register the 126 OpenPIC interrupts
         */
        for (i=0; i<126; i++) {
                struct interrupt template;
                char n[300];
                snprintf(n, sizeof(n), "%s.openpic.%i",
                    devinit->interrupt_path, i);
                memset(&template, 0, sizeof(template));
                template.line = 1 << i;
                template.name = n;
                template.extra = d;
                template.interrupt_assert = openpic_lo_interrupt_assert;
                template.interrupt_deassert = openpic_lo_interrupt_deassert;
                interrupt_handler_register(&template);
                debug("[ openpic: added interrupt %s ]\n", n);
        }

        memory_device_register(devinit->machine->memory, "openpic",
            devinit->addr, DEV_OPENPIC_LENGTH, dev_openpic_access, d, DM_DEFAULT, NULL);

        return 1;
}

1	dpavlin	22	/*
2	dpavlin	34	* Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
3	dpavlin	22	*
4			* Redistribution and use in source and binary forms, with or without
5			* modification, are permitted provided that the following conditions are met:
6			*
7			* 1. Redistributions of source code must retain the above copyright
8			* notice, this list of conditions and the following disclaimer.
9			* 2. Redistributions in binary form must reproduce the above copyright
10			* notice, this list of conditions and the following disclaimer in the
11			* documentation and/or other materials provided with the distribution.
12			* 3. The name of the author may not be used to endorse or promote products
13			* derived from this software without specific prior written permission.
14			*
15			* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16			* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17			* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18			* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19			* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20			* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21			* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22			* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23			* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24			* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25			* SUCH DAMAGE.
26			*
27	dpavlin	63	* $Id: dev_openpic.c,v 1.14 2007/09/11 21:42:52 debug Exp $
28	dpavlin	22	*
29	dpavlin	63	* COMMENT: OpenPIC Interrupt controller (used by sandpoint ppc)
30	dpavlin	64	* based on dev_gc.c
31	dpavlin	22	*/
32
33			#include <stdio.h>
34			#include <stdlib.h>
35			#include <string.h>
36
37			#include "cpu.h"
38			#include "device.h"
39			#include "machine.h"
40			#include "memory.h"
41			#include "misc.h"
42
43
44	dpavlin	63	#define DEV_OPENPIC_LENGTH 0x40000
45	dpavlin	34
46	dpavlin	63	struct openpic_data {
47	dpavlin	34	struct interrupt cpu_irq;
48
49			uint32_t status_hi;
50			uint32_t status_lo;
51			uint32_t enable_hi;
52			uint32_t enable_lo;
53			};
54
55
56	dpavlin	63	void openpic_hi_interrupt_assert(struct interrupt *interrupt)
57	dpavlin	34	{
58	dpavlin	63	struct openpic_data *d = interrupt->extra;
59	dpavlin	34	d->status_hi \|= interrupt->line;
60			if (d->status_lo & d->enable_lo \|\| d->status_hi & d->enable_hi)
61			INTERRUPT_ASSERT(d->cpu_irq);
62			}
63	dpavlin	63	void openpic_hi_interrupt_deassert(struct interrupt *interrupt)
64	dpavlin	34	{
65	dpavlin	63	struct openpic_data *d = interrupt->extra;
66	dpavlin	34	d->status_hi &= ~interrupt->line;
67			if (!(d->status_lo & d->enable_lo \|\| d->status_hi & d->enable_hi))
68			INTERRUPT_DEASSERT(d->cpu_irq);
69			}
70	dpavlin	63	void openpic_lo_interrupt_assert(struct interrupt *interrupt)
71	dpavlin	34	{
72	dpavlin	63	struct openpic_data *d = interrupt->extra;
73	dpavlin	34	d->status_lo \|= interrupt->line;
74			if (d->status_lo & d->enable_lo \|\| d->status_hi & d->enable_hi)
75			INTERRUPT_ASSERT(d->cpu_irq);
76			}
77	dpavlin	63	void openpic_lo_interrupt_deassert(struct interrupt *interrupt)
78	dpavlin	34	{
79	dpavlin	63	struct openpic_data *d = interrupt->extra;
80	dpavlin	34	d->status_lo &= ~interrupt->line;
81			if (!(d->status_lo & d->enable_lo \|\| d->status_hi & d->enable_hi))
82			INTERRUPT_DEASSERT(d->cpu_irq);
83			}
84
85	dpavlin	68	/*
86			* FIXME acitvity is never sat
87			*/
88
89	dpavlin	66	#define OPENPIC_MASK 0x80000000
90			#define OPENPIC_ACTIVITY 0x40000000 /* Read Only */
91			#define OPENPIC_PRIORITY_MASK 0x000f0000
92			#define OPENPIC_PRIORITY_SHIFT 16
93			#define OPENPIC_VECTOR_MASK 0x000000ff
94	dpavlin	34
95	dpavlin	66	#define OPENPIC_VEC_TIMER 64 /* and up */
96			#define OPENPIC_VEC_IPI 72 /* and up */
97			#define OPENPIC_VEC_SPURIOUS 127
98
99	dpavlin	67	#define OPENPIC_NUM_TIMERS 4
100			#define OPENPIC_NUM_IPI 4
101			#define OPENPIC_NUM_PRI 16
102			#define OPENPIC_NUM_VECTORS 256
103
104	dpavlin	63	DEVICE_ACCESS(openpic)
105	dpavlin	22	{
106	dpavlin	64	// struct openpic_data *d = extra;
107	dpavlin	68	uint64_t idata = 0, odata = 0;
108	dpavlin	22
109	dpavlin	67	if (writeflag == MEM_WRITE) {
110	dpavlin	22	idata = memory_readmax64(cpu, data, len);
111	dpavlin	68	// shuffle byte order
112			idata =
113	dpavlin	67	( idata & 0x000000ff ) << 24 \|
114			( idata & 0x0000ff00 ) << 8 \|
115			( idata & 0x00ff0000 ) >> 8 \|
116			( idata & 0xff000000 ) >> 24 ;
117	dpavlin	22
118	dpavlin	67	uint64_t priority,vector, active;
119	dpavlin	68	priority = ( idata & OPENPIC_PRIORITY_MASK ) >> OPENPIC_PRIORITY_SHIFT;
120			vector = ( idata & OPENPIC_VECTOR_MASK );
121			active = ( idata & OPENPIC_ACTIVITY );
122	dpavlin	66
123	dpavlin	68	debug("[ openpic: WRITE %05x \| %08x \| priority: %x vector: 0x%02x %d active: %x ]\n",
124			(int)relative_addr, (int)idata, (int)priority, (int)vector, (int)vector, (int)active );
125	dpavlin	67	}
126	dpavlin	66
127	dpavlin	22	switch (relative_addr) {
128
129	dpavlin	68	// version
130	dpavlin	65	case 0x00:
131	dpavlin	66	if (writeflag == MEM_READ) {
132	dpavlin	65	// version 1.2
133			odata = 0x02000000;
134	dpavlin	68	fatal("[ openpic: read version "
135			"offset 0x%x = %x]\n", (int)
136	dpavlin	66	relative_addr, (int)odata);
137			}
138			fatal("[ openpic: unimplemented write to "
139			"offset 0x%x: data=0x%x (OpenPIC version) ]\n", (int)
140			relative_addr, (int)idata);
141	dpavlin	65	break;
142
143	dpavlin	68	// global timer frequency
144			case 0xf0:
145			if (writeflag == MEM_READ) {
146			odata = 170 * 1000000; // MHz
147			fatal("[ openpic: read global timer frequency "
148			"offset 0x%x = %x]\n", (int)
149			relative_addr, (int)odata);
150			}
151			fatal("[ openpic: unimplemented write to "
152			"offset 0x%x: data=0x%x ]\n", (int)
153			relative_addr, (int)idata);
154			break;
155
156	dpavlin	22	#if 0
157			#define INT_STATE_REG_H (interrupt_reg + 0x00)
158			#define INT_ENABLE_REG_H (interrupt_reg + 0x04)
159			#define INT_CLEAR_REG_H (interrupt_reg + 0x08)
160			#define INT_LEVEL_REG_H (interrupt_reg + 0x0c)
161			#define INT_STATE_REG_L (interrupt_reg + 0x10)
162			#define INT_ENABLE_REG_L (interrupt_reg + 0x14)
163			#define INT_CLEAR_REG_L (interrupt_reg + 0x18)
164			#define INT_LEVEL_REG_L (interrupt_reg + 0x1c)
165
166			case 0x10:
167			if (writeflag == MEM_READ)
168	dpavlin	24	odata = d->status_hi & d->enable_hi;
169	dpavlin	22	break;
170
171			case 0x14:
172			if (writeflag == MEM_READ)
173			odata = d->enable_hi;
174			else {
175	dpavlin	34	int old_assert = (d->status_lo & d->enable_lo
176			\|\| d->status_hi & d->enable_hi);
177			int new_assert;
178	dpavlin	22	d->enable_hi = idata;
179	dpavlin	34
180			new_assert = (d->status_lo & d->enable_lo \|\|
181			d->status_hi & d->enable_hi);
182
183			if (old_assert && !new_assert)
184			INTERRUPT_DEASSERT(d->cpu_irq);
185			else if (!old_assert && new_assert)
186			INTERRUPT_ASSERT(d->cpu_irq);
187	dpavlin	22	}
188			break;
189
190			case 0x18:
191			if (writeflag == MEM_WRITE) {
192	dpavlin	34	int old_assert = (d->status_lo & d->enable_lo
193			\|\| d->status_hi & d->enable_hi);
194			int new_assert;
195	dpavlin	22	d->status_hi &= ~idata;
196	dpavlin	34
197			new_assert = (d->status_lo & d->enable_lo \|\|
198			d->status_hi & d->enable_hi);
199
200			if (old_assert && !new_assert)
201			INTERRUPT_DEASSERT(d->cpu_irq);
202			else if (!old_assert && new_assert)
203			INTERRUPT_ASSERT(d->cpu_irq);
204	dpavlin	22	}
205			break;
206
207			case 0x20:
208			if (writeflag == MEM_READ)
209	dpavlin	24	odata = d->status_lo & d->enable_lo;
210	dpavlin	22	break;
211
212			case 0x24:
213			if (writeflag == MEM_READ)
214			odata = d->enable_lo;
215			else {
216	dpavlin	34	int old_assert = (d->status_lo & d->enable_lo
217			\|\| d->status_hi & d->enable_hi);
218			int new_assert;
219	dpavlin	22	d->enable_lo = idata;
220	dpavlin	34
221			new_assert = (d->status_lo & d->enable_lo \|\|
222			d->status_hi & d->enable_hi);
223
224			if (old_assert && !new_assert)
225			INTERRUPT_DEASSERT(d->cpu_irq);
226			else if (!old_assert && new_assert)
227			INTERRUPT_ASSERT(d->cpu_irq);
228	dpavlin	22	}
229			break;
230
231			case 0x28:
232			if (writeflag == MEM_WRITE) {
233	dpavlin	34	int old_assert = (d->status_lo & d->enable_lo
234			\|\| d->status_hi & d->enable_hi);
235			int new_assert;
236	dpavlin	22	d->status_lo &= ~idata;
237	dpavlin	34
238			new_assert = (d->status_lo & d->enable_lo \|\|
239			d->status_hi & d->enable_hi);
240
241			if (old_assert && !new_assert)
242			INTERRUPT_DEASSERT(d->cpu_irq);
243			else if (!old_assert && new_assert)
244			INTERRUPT_ASSERT(d->cpu_irq);
245	dpavlin	22	}
246			break;
247
248	dpavlin	44	case 0x1c:
249	dpavlin	24	case 0x2c:
250	dpavlin	34	/* Avoid a debug message. */
251	dpavlin	24	break;
252	dpavlin	64	#endif
253	dpavlin	68	default:
254			if (writeflag == MEM_WRITE) {
255	dpavlin	63	fatal("[ openpic: unimplemented write to "
256	dpavlin	68	"offset 0x%x idata = %x ]\n",
257			(int)relative_addr, (int)idata
258			);
259	dpavlin	22	} else {
260	dpavlin	63	fatal("[ openpic: unimplemented read from "
261	dpavlin	68	"offset 0x%x odata = %x ]\n",
262			(int)relative_addr, (int)odata
263			);
264	dpavlin	22	}
265			}
266
267	dpavlin	68	if (writeflag == MEM_READ) {
268			// shuffle byte order
269			odata =
270			( odata & 0x000000ff ) << 24 \|
271			( odata & 0x0000ff00 ) << 8 \|
272			( odata & 0x00ff0000 ) >> 8 \|
273			( odata & 0xff000000 ) >> 24 ;
274	dpavlin	22	memory_writemax64(cpu, data, len, odata);
275	dpavlin	68	debug("[ openpic: READ %05x \| %08x ]\n",
276			(int)relative_addr, (int)odata
277			);
278			}
279	dpavlin	22
280			return 1;
281			}
282
283
284	dpavlin	63	DEVINIT(openpic)
285	dpavlin	22	{
286	dpavlin	63	struct openpic_data *d;
287	dpavlin	34	int i;
288	dpavlin	22
289	dpavlin	63	CHECK_ALLOCATION(d = malloc(sizeof(struct openpic_data)));
290			memset(d, 0, sizeof(struct openpic_data));
291	dpavlin	22
292	dpavlin	42	/* Connect to the CPU interrupt pin: */
293	dpavlin	34	INTERRUPT_CONNECT(devinit->interrupt_path, d->cpu_irq);
294	dpavlin	22
295	dpavlin	34	/*
296	dpavlin	64	* Register the 126 OpenPIC interrupts
297	dpavlin	34	*/
298	dpavlin	64	for (i=0; i<126; i++) {
299	dpavlin	34	struct interrupt template;
300			char n[300];
301	dpavlin	64	snprintf(n, sizeof(n), "%s.openpic.%i",
302	dpavlin	34	devinit->interrupt_path, i);
303			memset(&template, 0, sizeof(template));
304			template.line = 1 << i;
305			template.name = n;
306			template.extra = d;
307	dpavlin	63	template.interrupt_assert = openpic_lo_interrupt_assert;
308			template.interrupt_deassert = openpic_lo_interrupt_deassert;
309	dpavlin	34	interrupt_handler_register(&template);
310	dpavlin	68	debug("[ openpic: added interrupt %s ]\n", n);
311	dpavlin	34	}
312
313	dpavlin	63	memory_device_register(devinit->machine->memory, "openpic",
314			devinit->addr, DEV_OPENPIC_LENGTH, dev_openpic_access, d, DM_DEFAULT, NULL);
315	dpavlin	34
316			return 1;
317	dpavlin	22	}
318