/[gxemul]/trunk/src/devices/dev_openpic.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Annotation of /trunk/src/devices/dev_openpic.c

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Revision 64 - (hide annotations)
Sat Oct 13 15:43:48 2007 UTC (13 years, 8 months ago) by dpavlin
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File size: 6874 byte(s)
make it compile and few tweaks
1 dpavlin 22 /*
2 dpavlin 34 * Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
3 dpavlin 22 *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27 dpavlin 63 * $Id: dev_openpic.c,v 1.14 2007/09/11 21:42:52 debug Exp $
28 dpavlin 22 *
29 dpavlin 63 * COMMENT: OpenPIC Interrupt controller (used by sandpoint ppc)
30 dpavlin 64 * based on dev_gc.c
31 dpavlin 22 */
32    
33     #include <stdio.h>
34     #include <stdlib.h>
35     #include <string.h>
36    
37     #include "cpu.h"
38     #include "device.h"
39     #include "machine.h"
40     #include "memory.h"
41     #include "misc.h"
42    
43    
44 dpavlin 63 #define DEV_OPENPIC_LENGTH 0x40000
45 dpavlin 34
46 dpavlin 63 struct openpic_data {
47 dpavlin 34 struct interrupt cpu_irq;
48    
49     uint32_t status_hi;
50     uint32_t status_lo;
51     uint32_t enable_hi;
52     uint32_t enable_lo;
53     };
54    
55    
56 dpavlin 63 void openpic_hi_interrupt_assert(struct interrupt *interrupt)
57 dpavlin 34 {
58 dpavlin 63 struct openpic_data *d = interrupt->extra;
59 dpavlin 34 d->status_hi |= interrupt->line;
60     if (d->status_lo & d->enable_lo || d->status_hi & d->enable_hi)
61     INTERRUPT_ASSERT(d->cpu_irq);
62     }
63 dpavlin 63 void openpic_hi_interrupt_deassert(struct interrupt *interrupt)
64 dpavlin 34 {
65 dpavlin 63 struct openpic_data *d = interrupt->extra;
66 dpavlin 34 d->status_hi &= ~interrupt->line;
67     if (!(d->status_lo & d->enable_lo || d->status_hi & d->enable_hi))
68     INTERRUPT_DEASSERT(d->cpu_irq);
69     }
70 dpavlin 63 void openpic_lo_interrupt_assert(struct interrupt *interrupt)
71 dpavlin 34 {
72 dpavlin 63 struct openpic_data *d = interrupt->extra;
73 dpavlin 34 d->status_lo |= interrupt->line;
74     if (d->status_lo & d->enable_lo || d->status_hi & d->enable_hi)
75     INTERRUPT_ASSERT(d->cpu_irq);
76     }
77 dpavlin 63 void openpic_lo_interrupt_deassert(struct interrupt *interrupt)
78 dpavlin 34 {
79 dpavlin 63 struct openpic_data *d = interrupt->extra;
80 dpavlin 34 d->status_lo &= ~interrupt->line;
81     if (!(d->status_lo & d->enable_lo || d->status_hi & d->enable_hi))
82     INTERRUPT_DEASSERT(d->cpu_irq);
83     }
84    
85    
86 dpavlin 63 DEVICE_ACCESS(openpic)
87 dpavlin 22 {
88 dpavlin 64 // struct openpic_data *d = extra;
89 dpavlin 22 uint64_t idata = 0, odata = 0;
90    
91     if (writeflag == MEM_WRITE)
92     idata = memory_readmax64(cpu, data, len);
93    
94     switch (relative_addr) {
95    
96     #if 0
97     #define INT_STATE_REG_H (interrupt_reg + 0x00)
98     #define INT_ENABLE_REG_H (interrupt_reg + 0x04)
99     #define INT_CLEAR_REG_H (interrupt_reg + 0x08)
100     #define INT_LEVEL_REG_H (interrupt_reg + 0x0c)
101     #define INT_STATE_REG_L (interrupt_reg + 0x10)
102     #define INT_ENABLE_REG_L (interrupt_reg + 0x14)
103     #define INT_CLEAR_REG_L (interrupt_reg + 0x18)
104     #define INT_LEVEL_REG_L (interrupt_reg + 0x1c)
105     #endif
106    
107 dpavlin 64 #if 0
108 dpavlin 22 case 0x10:
109     if (writeflag == MEM_READ)
110 dpavlin 24 odata = d->status_hi & d->enable_hi;
111 dpavlin 22 break;
112    
113     case 0x14:
114     if (writeflag == MEM_READ)
115     odata = d->enable_hi;
116     else {
117 dpavlin 34 int old_assert = (d->status_lo & d->enable_lo
118     || d->status_hi & d->enable_hi);
119     int new_assert;
120 dpavlin 22 d->enable_hi = idata;
121 dpavlin 34
122     new_assert = (d->status_lo & d->enable_lo ||
123     d->status_hi & d->enable_hi);
124    
125     if (old_assert && !new_assert)
126     INTERRUPT_DEASSERT(d->cpu_irq);
127     else if (!old_assert && new_assert)
128     INTERRUPT_ASSERT(d->cpu_irq);
129 dpavlin 22 }
130     break;
131    
132     case 0x18:
133     if (writeflag == MEM_WRITE) {
134 dpavlin 34 int old_assert = (d->status_lo & d->enable_lo
135     || d->status_hi & d->enable_hi);
136     int new_assert;
137 dpavlin 22 d->status_hi &= ~idata;
138 dpavlin 34
139     new_assert = (d->status_lo & d->enable_lo ||
140     d->status_hi & d->enable_hi);
141    
142     if (old_assert && !new_assert)
143     INTERRUPT_DEASSERT(d->cpu_irq);
144     else if (!old_assert && new_assert)
145     INTERRUPT_ASSERT(d->cpu_irq);
146 dpavlin 22 }
147     break;
148    
149     case 0x20:
150     if (writeflag == MEM_READ)
151 dpavlin 24 odata = d->status_lo & d->enable_lo;
152 dpavlin 22 break;
153    
154     case 0x24:
155     if (writeflag == MEM_READ)
156     odata = d->enable_lo;
157     else {
158 dpavlin 34 int old_assert = (d->status_lo & d->enable_lo
159     || d->status_hi & d->enable_hi);
160     int new_assert;
161 dpavlin 22 d->enable_lo = idata;
162 dpavlin 34
163     new_assert = (d->status_lo & d->enable_lo ||
164     d->status_hi & d->enable_hi);
165    
166     if (old_assert && !new_assert)
167     INTERRUPT_DEASSERT(d->cpu_irq);
168     else if (!old_assert && new_assert)
169     INTERRUPT_ASSERT(d->cpu_irq);
170 dpavlin 22 }
171     break;
172    
173     case 0x28:
174     if (writeflag == MEM_WRITE) {
175 dpavlin 34 int old_assert = (d->status_lo & d->enable_lo
176     || d->status_hi & d->enable_hi);
177     int new_assert;
178 dpavlin 22 d->status_lo &= ~idata;
179 dpavlin 34
180     new_assert = (d->status_lo & d->enable_lo ||
181     d->status_hi & d->enable_hi);
182    
183     if (old_assert && !new_assert)
184     INTERRUPT_DEASSERT(d->cpu_irq);
185     else if (!old_assert && new_assert)
186     INTERRUPT_ASSERT(d->cpu_irq);
187 dpavlin 22 }
188     break;
189    
190 dpavlin 44 case 0x1c:
191 dpavlin 24 case 0x2c:
192 dpavlin 34 /* Avoid a debug message. */
193 dpavlin 24 break;
194 dpavlin 64 #endif
195 dpavlin 22 default:if (writeflag == MEM_WRITE) {
196 dpavlin 63 fatal("[ openpic: unimplemented write to "
197 dpavlin 22 "offset 0x%x: data=0x%x ]\n", (int)
198     relative_addr, (int)idata);
199     } else {
200 dpavlin 63 fatal("[ openpic: unimplemented read from "
201 dpavlin 22 "offset 0x%x ]\n", (int)relative_addr);
202     }
203     }
204    
205     if (writeflag == MEM_READ)
206     memory_writemax64(cpu, data, len, odata);
207    
208     return 1;
209     }
210    
211    
212 dpavlin 63 DEVINIT(openpic)
213 dpavlin 22 {
214 dpavlin 63 struct openpic_data *d;
215 dpavlin 34 int i;
216 dpavlin 22
217 dpavlin 63 CHECK_ALLOCATION(d = malloc(sizeof(struct openpic_data)));
218     memset(d, 0, sizeof(struct openpic_data));
219 dpavlin 22
220 dpavlin 42 /* Connect to the CPU interrupt pin: */
221 dpavlin 34 INTERRUPT_CONNECT(devinit->interrupt_path, d->cpu_irq);
222 dpavlin 22
223 dpavlin 34 /*
224 dpavlin 64 * Register the 126 OpenPIC interrupts
225 dpavlin 34 */
226 dpavlin 64 for (i=0; i<126; i++) {
227 dpavlin 34 struct interrupt template;
228     char n[300];
229 dpavlin 64 snprintf(n, sizeof(n), "%s.openpic.%i",
230 dpavlin 34 devinit->interrupt_path, i);
231     memset(&template, 0, sizeof(template));
232     template.line = 1 << i;
233     template.name = n;
234     template.extra = d;
235 dpavlin 63 template.interrupt_assert = openpic_lo_interrupt_assert;
236     template.interrupt_deassert = openpic_lo_interrupt_deassert;
237 dpavlin 34 interrupt_handler_register(&template);
238     }
239    
240 dpavlin 63 memory_device_register(devinit->machine->memory, "openpic",
241     devinit->addr, DEV_OPENPIC_LENGTH, dev_openpic_access, d, DM_DEFAULT, NULL);
242 dpavlin 34
243     return 1;
244 dpavlin 22 }
245    

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