/[gxemul]/trunk/src/devices/dev_openpic.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Annotation of /trunk/src/devices/dev_openpic.c

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Revision 42 - (hide annotations)
Mon Oct 8 16:22:32 2007 UTC (13 years, 8 months ago) by dpavlin
Original Path: trunk/src/devices/dev_gc.c
File MIME type: text/plain
File size: 7061 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1613 2007/06/15 20:11:26 debug Exp $
20070501	Continuing a little on m88k disassembly (control registers,
		more instructions).
		Adding a dummy mvme88k machine mode.
20070502	Re-adding MIPS load/store alignment exceptions.
20070503	Implementing more of the M88K disassembly code.
20070504	Adding disassembly of some more M88K load/store instructions.
		Implementing some relatively simple M88K instructions (br.n,
		xor[.u] imm, and[.u] imm).
20070505	Implementing M88K three-register and, or, xor, and jmp[.n],
		bsr[.n] including function call trace stuff.
		Applying a patch from Bruce M. Simpson which implements the
		SYSCON_BOARD_CPU_CLOCK_FREQ_ID object of the syscon call in
		the yamon PROM emulation.
20070506	Implementing M88K bb0[.n] and bb1[.n], and skeletons for
		ldcr and stcr (although no control regs are implemented yet).
20070509	Found and fixed the bug which caused Linux for QEMU_MIPS to
		stop working in 0.4.5.1: It was a faulty change to the MIPS
		'sc' and 'scd' instructions I made while going through gcc -W
		warnings on 20070428.
20070510	Updating the Linux/QEMU_MIPS section in guestoses.html to
		use mips-test-0.2.tar.gz instead of 0.1.
		A big thank you to Miod Vallat for sending me M88K manuals.
		Implementing more M88K instructions (addu, subu, div[u], mulu,
		ext[u], clr, set, cmp).
20070511	Fixing bugs in the M88K "and" and "and.u" instructions (found
		by comparing against the manual).
		Implementing more M88K instructions (mask[.u], mak, bcnd (auto-
		generated)) and some more control register details.
		Cleanup: Removing the experimental AVR emulation mode and
		corresponding devices; AVR emulation wasn't really meaningful.
		Implementing autogeneration of most M88K loads/stores. The
		rectangle drawing demo (with -O0) for M88K runs :-)
		Beginning on M88K exception handling.
		More M88K instructions: tb0, tb1, rte, sub, jsr[.n].
		Adding some skeleton MVME PROM ("BUG") emulation.
20070512	Fixing a bug in the M88K cmp instruction.
		Adding the M88K lda (scaled register) instruction.
		Fixing bugs in 64-bit (32-bit pairs) M88K loads/stores.
		Removing the unused tick_hz stuff from the machine struct.
		Implementing the M88K xmem instruction. OpenBSD/mvme88k gets
		far enough to display the Copyright banner :-)
		Implementing subu.co (guess), addu.co, addu.ci, ff0, and ff1.
		Adding a dev_mvme187, for MVME187-specific devices/registers.
		OpenBSD/mvme88k prints more boot messages. :)
20070515	Continuing on MVME187 emulation (adding more devices, beginning
		on the CMMUs, etc).
		Adding the M88K and.c, xor.c, and or.c instructions, and making
		sure that mul, div, etc cause exceptions if executed when SFD1
		is disabled.
20070517	Continuing on M88K and MVME187 emulation in general; moving
		the CMMU registers to the CPU struct, separating dev_pcc2 from
		dev_mvme187, and beginning on memory_m88k.c (BATC and PATC).
		Fixing a bug in 64-bit (32-bit pairs) M88K fast stores.
		Implementing the clock part of dev_mk48txx.
		Implementing the M88K fstcr and xcr instructions.
		Implementing m88k_cpu_tlbdump().
		Beginning on the implementation of a separate address space
		for M88K .usr loads/stores.
20070520	Removing the non-working (skeleton) Sandpoint, SonyNEWS, SHARK
		Dnard, and Zaurus machine modes.
		Experimenting with dyntrans to_be_translated read-ahead. It
		seems to give a very small performance increase for MIPS
		emulation, but a large performance degradation for SuperH. Hm.
20070522	Disabling correct SuperH ITLB emulation; it does not seem to be
		necessary in order to let SH4 guest OSes run, and it slows down
		userspace code.
		Implementing "samepage" branches for SuperH emulation, and some
		other minor speed hacks.
20070525	Continuing on M88K memory-related stuff: exceptions, memory
		transaction register contents, etc.
		Implementing the M88K subu.ci instruction.
		Removing the non-working (skeleton) Iyonix machine mode.
		OpenBSD/mvme88k reaches userland :-), starts executing
		/sbin/init's instructions, and issues a few syscalls, before
		crashing.
20070526	Fixing bugs in dev_mk48txx, so that OpenBSD/mvme88k detects
		the correct time-of-day.
		Implementing a generic IRQ controller for the test machines
		(dev_irqc), similar to a proposed patch from Petr Stepan.
		Experimenting some more with translation read-ahead.
		Adding an "expect" script for automated OpenBSD/landisk
		install regression/performance tests.
20070527	Adding a dummy mmEye (SH3) machine mode skeleton.
		FINALLY found the strange M88K bug I have been hunting: I had
		not emulated the SNIP value for exceptions occurring in
		branch delay slots correctly.
		Implementing correct exceptions for 64-bit M88K loads/stores.
		Address to symbol lookups are now disabled when M88K is
		running in usermode (because usermode addresses don't have
		anything to do with supervisor addresses).
20070531	Removing the mmEye machine mode skeleton.
20070604	Some minor code cleanup.
20070605	Moving src/useremul.c into a subdir (src/useremul/), and
		cleaning up some more legacy constructs.
		Adding -Wstrict-aliasing and -fstrict-aliasing detection to
		the configure script.
20070606	Adding a check for broken GCC on Solaris to the configure
		script. (GCC 3.4.3 on Solaris cannot handle static variables
		which are initialized to 0 or NULL. :-/)
		Removing the old (non-working) ARC emulation modes: NEC RD94,
		R94, R96, and R98, and the last traces of Olivetti M700 and
		Deskstation Tyne.
		Removing the non-working skeleton WDSC device (dev_wdsc).
20070607	Thinking about how to use the host's cc + ld at runtime to
		generate native code. (See experiments/native_cc_ld_test.i
		for an example.)
20070608	Adding a program counter sampling timer, which could be useful
		for native code generation experiments.
		The KN02_CSR_NRMMOD bit in the DECstation 5000/200 (KN02) CSR
		should always be set, to allow a 5000/200 PROM to boot.
20070609	Moving out breakpoint details from the machine struct into
		a helper struct, and removing the limit on max nr of
		breakpoints.
20070610	Moving out tick functions into a helper struct as well (which
		also gets rid of the max limit).
20070612	FINALLY figured out why Debian/DECstation stopped working when
		translation read-ahead was enabled: in src/memory_rw.c, the
		call to invalidate_code_translation was made also if the
		memory access was an instruction load (if the page was mapped
		as writable); it shouldn't be called in that case.
20070613	Implementing some more MIPS32/64 revision 2 instructions: di,
		ei, ext, dext, dextm, dextu, and ins.
20070614	Implementing an instruction combination for the NetBSD/arm
		idle loop (making the host not use any cpu if NetBSD/arm
		inside the emulator is not using any cpu).
		Increasing the nr of ARM VPH entries from 128 to 384.
20070615	Removing the ENABLE_arch stuff from the configure script, so
		that all included architectures are included in both release
		and development builds.
		Moving memory related helper functions from misc.c to memory.c.
		Adding preliminary instructions for netbooting NetBSD/pmppc to
		guestoses.html; it doesn't work yet, there are weird timeouts.
		Beginning a total rewrite of the userland emulation modes
		(removing all emulation modes, beginning from scratch with
		NetBSD/MIPS and FreeBSD/Alpha only).
20070616	After fixing a bug in the DEC21143 NIC (the TDSTAT_OWN bit was
		only cleared for the last segment when transmitting, not all
		segments), NetBSD/pmppc boots with root-on-nfs without the
		timeouts. Updating guestoses.html.
		Removing the skeleton PSP (Playstation Portable) mode.
		Moving X11-related stuff in the machine struct into a helper
		struct.
		Cleanup of out-of-memory checks, to use a new CHECK_ALLOCATION
		macro (which prints a meaningful error message).
		Adding a COMMENT to each machine and device (for automagic
		.index comment generation).
		Doing regression testing for the next release.

==============  RELEASE 0.4.6  ==============


1 dpavlin 22 /*
2 dpavlin 34 * Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
3 dpavlin 22 *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27 dpavlin 42 * $Id: dev_gc.c,v 1.13 2007/06/15 19:11:15 debug Exp $
28 dpavlin 22 *
29 dpavlin 42 * COMMENT: Grand Central Interrupt controller (used by MacPPC)
30 dpavlin 22 */
31    
32     #include <stdio.h>
33     #include <stdlib.h>
34     #include <string.h>
35    
36     #include "cpu.h"
37     #include "device.h"
38     #include "machine.h"
39     #include "memory.h"
40     #include "misc.h"
41    
42    
43 dpavlin 34 #define DEV_GC_LENGTH 0x100
44    
45     struct gc_data {
46     struct interrupt cpu_irq;
47    
48     uint32_t status_hi;
49     uint32_t status_lo;
50     uint32_t enable_hi;
51     uint32_t enable_lo;
52     };
53    
54    
55     void gc_hi_interrupt_assert(struct interrupt *interrupt)
56     {
57     struct gc_data *d = interrupt->extra;
58     d->status_hi |= interrupt->line;
59     if (d->status_lo & d->enable_lo || d->status_hi & d->enable_hi)
60     INTERRUPT_ASSERT(d->cpu_irq);
61     }
62     void gc_hi_interrupt_deassert(struct interrupt *interrupt)
63     {
64     struct gc_data *d = interrupt->extra;
65     d->status_hi &= ~interrupt->line;
66     if (!(d->status_lo & d->enable_lo || d->status_hi & d->enable_hi))
67     INTERRUPT_DEASSERT(d->cpu_irq);
68     }
69     void gc_lo_interrupt_assert(struct interrupt *interrupt)
70     {
71     struct gc_data *d = interrupt->extra;
72     d->status_lo |= interrupt->line;
73     if (d->status_lo & d->enable_lo || d->status_hi & d->enable_hi)
74     INTERRUPT_ASSERT(d->cpu_irq);
75     }
76     void gc_lo_interrupt_deassert(struct interrupt *interrupt)
77     {
78     struct gc_data *d = interrupt->extra;
79     d->status_lo &= ~interrupt->line;
80     if (!(d->status_lo & d->enable_lo || d->status_hi & d->enable_hi))
81     INTERRUPT_DEASSERT(d->cpu_irq);
82     }
83    
84    
85 dpavlin 22 DEVICE_ACCESS(gc)
86     {
87     struct gc_data *d = extra;
88     uint64_t idata = 0, odata = 0;
89    
90     if (writeflag == MEM_WRITE)
91     idata = memory_readmax64(cpu, data, len);
92    
93     switch (relative_addr) {
94    
95     #if 0
96     #define INT_STATE_REG_H (interrupt_reg + 0x00)
97     #define INT_ENABLE_REG_H (interrupt_reg + 0x04)
98     #define INT_CLEAR_REG_H (interrupt_reg + 0x08)
99     #define INT_LEVEL_REG_H (interrupt_reg + 0x0c)
100     #define INT_STATE_REG_L (interrupt_reg + 0x10)
101     #define INT_ENABLE_REG_L (interrupt_reg + 0x14)
102     #define INT_CLEAR_REG_L (interrupt_reg + 0x18)
103     #define INT_LEVEL_REG_L (interrupt_reg + 0x1c)
104     #endif
105    
106     case 0x10:
107     if (writeflag == MEM_READ)
108 dpavlin 24 odata = d->status_hi & d->enable_hi;
109 dpavlin 22 break;
110    
111     case 0x14:
112     if (writeflag == MEM_READ)
113     odata = d->enable_hi;
114     else {
115 dpavlin 34 int old_assert = (d->status_lo & d->enable_lo
116     || d->status_hi & d->enable_hi);
117     int new_assert;
118 dpavlin 22 d->enable_hi = idata;
119 dpavlin 34
120     new_assert = (d->status_lo & d->enable_lo ||
121     d->status_hi & d->enable_hi);
122    
123     if (old_assert && !new_assert)
124     INTERRUPT_DEASSERT(d->cpu_irq);
125     else if (!old_assert && new_assert)
126     INTERRUPT_ASSERT(d->cpu_irq);
127 dpavlin 22 }
128     break;
129    
130     case 0x18:
131     if (writeflag == MEM_WRITE) {
132 dpavlin 34 int old_assert = (d->status_lo & d->enable_lo
133     || d->status_hi & d->enable_hi);
134     int new_assert;
135 dpavlin 22 d->status_hi &= ~idata;
136 dpavlin 34
137     new_assert = (d->status_lo & d->enable_lo ||
138     d->status_hi & d->enable_hi);
139    
140     if (old_assert && !new_assert)
141     INTERRUPT_DEASSERT(d->cpu_irq);
142     else if (!old_assert && new_assert)
143     INTERRUPT_ASSERT(d->cpu_irq);
144 dpavlin 22 }
145     break;
146    
147     case 0x20:
148     if (writeflag == MEM_READ)
149 dpavlin 24 odata = d->status_lo & d->enable_lo;
150 dpavlin 22 break;
151    
152     case 0x24:
153     if (writeflag == MEM_READ)
154     odata = d->enable_lo;
155     else {
156 dpavlin 34 int old_assert = (d->status_lo & d->enable_lo
157     || d->status_hi & d->enable_hi);
158     int new_assert;
159 dpavlin 22 d->enable_lo = idata;
160 dpavlin 34
161     new_assert = (d->status_lo & d->enable_lo ||
162     d->status_hi & d->enable_hi);
163    
164     if (old_assert && !new_assert)
165     INTERRUPT_DEASSERT(d->cpu_irq);
166     else if (!old_assert && new_assert)
167     INTERRUPT_ASSERT(d->cpu_irq);
168 dpavlin 22 }
169     break;
170    
171     case 0x28:
172     if (writeflag == MEM_WRITE) {
173 dpavlin 34 int old_assert = (d->status_lo & d->enable_lo
174     || d->status_hi & d->enable_hi);
175     int new_assert;
176 dpavlin 22 d->status_lo &= ~idata;
177 dpavlin 34
178     new_assert = (d->status_lo & d->enable_lo ||
179     d->status_hi & d->enable_hi);
180    
181     if (old_assert && !new_assert)
182     INTERRUPT_DEASSERT(d->cpu_irq);
183     else if (!old_assert && new_assert)
184     INTERRUPT_ASSERT(d->cpu_irq);
185 dpavlin 22 }
186     break;
187    
188 dpavlin 24 case 0x2c:
189 dpavlin 34 /* Avoid a debug message. */
190 dpavlin 24 break;
191    
192 dpavlin 22 default:if (writeflag == MEM_WRITE) {
193     fatal("[ gc: unimplemented write to "
194     "offset 0x%x: data=0x%x ]\n", (int)
195     relative_addr, (int)idata);
196     } else {
197     fatal("[ gc: unimplemented read from "
198     "offset 0x%x ]\n", (int)relative_addr);
199     }
200     }
201    
202     if (writeflag == MEM_READ)
203     memory_writemax64(cpu, data, len, odata);
204    
205     return 1;
206     }
207    
208    
209 dpavlin 34 DEVINIT(gc)
210 dpavlin 22 {
211     struct gc_data *d;
212 dpavlin 34 int i;
213 dpavlin 22
214 dpavlin 42 CHECK_ALLOCATION(d = malloc(sizeof(struct gc_data)));
215 dpavlin 22 memset(d, 0, sizeof(struct gc_data));
216    
217 dpavlin 42 /* Connect to the CPU interrupt pin: */
218 dpavlin 34 INTERRUPT_CONNECT(devinit->interrupt_path, d->cpu_irq);
219 dpavlin 22
220 dpavlin 34 /*
221     * Register the 64 Grand Central interrupts (32 lo, 32 hi):
222     */
223     for (i=0; i<32; i++) {
224     struct interrupt template;
225     char n[300];
226     snprintf(n, sizeof(n), "%s.gc.lo.%i",
227     devinit->interrupt_path, i);
228     memset(&template, 0, sizeof(template));
229     template.line = 1 << i;
230     template.name = n;
231     template.extra = d;
232     template.interrupt_assert = gc_lo_interrupt_assert;
233     template.interrupt_deassert = gc_lo_interrupt_deassert;
234     interrupt_handler_register(&template);
235    
236     snprintf(n, sizeof(n), "%s.gc.hi.%i",
237     devinit->interrupt_path, i);
238     memset(&template, 0, sizeof(template));
239     template.line = 1 << i;
240     template.name = n;
241     template.extra = d;
242     template.interrupt_assert = gc_hi_interrupt_assert;
243     template.interrupt_deassert = gc_hi_interrupt_deassert;
244     interrupt_handler_register(&template);
245     }
246    
247     memory_device_register(devinit->machine->memory, "gc",
248     devinit->addr, DEV_GC_LENGTH, dev_gc_access, d, DM_DEFAULT, NULL);
249    
250     return 1;
251 dpavlin 22 }
252    

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