/[gxemul]/trunk/src/devices/dev_gt.c
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revision 32 by dpavlin, Mon Oct 8 16:20:58 2007 UTC revision 44 by dpavlin, Mon Oct 8 16:22:56 2007 UTC
# Line 1  Line 1 
1  /*  /*
2   *  Copyright (C) 2003-2006  Anders Gavare.  All rights reserved.   *  Copyright (C) 2003-2007  Anders Gavare.  All rights reserved.
3   *   *
4   *  Redistribution and use in source and binary forms, with or without   *  Redistribution and use in source and binary forms, with or without
5   *  modification, are permitted provided that the following conditions are met:   *  modification, are permitted provided that the following conditions are met:
# Line 25  Line 25 
25   *  SUCH DAMAGE.   *  SUCH DAMAGE.
26   *     *  
27   *   *
28   *  $Id: dev_gt.c,v 1.44 2006/09/23 03:52:10 debug Exp $   *  $Id: dev_gt.c,v 1.53 2007/06/16 05:09:55 debug Exp $
29   *     *  
30   *  Galileo Technology GT-64xxx PCI controller.   *  COMMENT: Galileo Technology GT-64xxx PCI controller
31   *   *
32   *      GT-64011        Used in Cobalt machines.   *      GT-64011        Used in Cobalt machines.
33   *      GT-64120        Used in evbmips machines (Malta).   *      GT-64120        Used in evbmips machines (Malta).
# Line 41  Line 41 
41  #include "bus_pci.h"  #include "bus_pci.h"
42  #include "cpu.h"  #include "cpu.h"
43  #include "devices.h"  #include "devices.h"
44    #include "interrupt.h"
45  #include "machine.h"  #include "machine.h"
46  #include "memory.h"  #include "memory.h"
47  #include "misc.h"  #include "misc.h"
# Line 59  Line 60 
60    
61    
62  struct gt_data {  struct gt_data {
         int             pci_irqbase;  
63          int             type;          int             type;
64    
65          struct timer    *timer;          struct timer    *timer;
66          int             timer0_irqnr;          struct interrupt timer0_irq;
67          int             interrupt_hz;          int             interrupt_hz;
68          int             pending_timer0_interrupts;          int             pending_timer0_interrupts;
69    
# Line 81  struct gt_data { Line 81  struct gt_data {
81   */   */
82  static void timer_tick(struct timer *timer, void *extra)  static void timer_tick(struct timer *timer, void *extra)
83  {  {
84          struct gt_data *d = (struct gt_data *) extra;          struct gt_data *d = extra;
85          d->pending_timer0_interrupts ++;          d->pending_timer0_interrupts ++;
86  }  }
87    
88    
89  DEVICE_TICK(gt)  DEVICE_TICK(gt)
90  {  {
91          struct gt_data *d = (struct gt_data *) extra;          struct gt_data *d = extra;
   
92          if (d->pending_timer0_interrupts > 0)          if (d->pending_timer0_interrupts > 0)
93                  cpu_interrupt(cpu, d->timer0_irqnr);                  INTERRUPT_ASSERT(d->timer0_irq);
94  }  }
95    
96    
97  DEVICE_ACCESS(gt)  DEVICE_ACCESS(gt)
98  {  {
99            struct gt_data *d = extra;
100          uint64_t idata = 0, odata = 0;          uint64_t idata = 0, odata = 0;
101          int bus, dev, func, reg;          int bus, dev, func, reg;
102          size_t i;          size_t i;
         struct gt_data *d = extra;  
103    
104          if (writeflag == MEM_WRITE)          if (writeflag == MEM_WRITE)
105                  idata = memory_readmax64(cpu, data, len);                  idata = memory_readmax64(cpu, data, len);
# Line 144  DEVICE_ACCESS(gt) Line 143  DEVICE_ACCESS(gt)
143                          return 1;                          return 1;
144                  } else {                  } else {
145                          odata = GTIC_T0EXP;                          odata = GTIC_T0EXP;
146                          cpu_interrupt_ack(cpu, d->timer0_irqnr);                          INTERRUPT_DEASSERT(d->timer0_irq);
147    
148                          if (d->pending_timer0_interrupts > 0)                          if (d->pending_timer0_interrupts > 0)
149                                  d->pending_timer0_interrupts --;                                  d->pending_timer0_interrupts --;
# Line 156  DEVICE_ACCESS(gt) Line 155  DEVICE_ACCESS(gt)
155    
156          case GT_PCI0_INTR_ACK:          case GT_PCI0_INTR_ACK:
157                  odata = cpu->machine->isa_pic_data.last_int;                  odata = cpu->machine->isa_pic_data.last_int;
158                  cpu_interrupt_ack(cpu, d->pci_irqbase + odata);                  /*  TODO: Actually ack the interrupt?  */
159                  break;                  break;
160    
161          case GT_TIMER_CTRL:          case GT_TIMER_CTRL:
# Line 218  DEVICE_ACCESS(gt) Line 217  DEVICE_ACCESS(gt)
217   *  is added to the bus, then a pointer to the bus is returned.   *  is added to the bus, then a pointer to the bus is returned.
218   */   */
219  struct pci_data *dev_gt_init(struct machine *machine, struct memory *mem,  struct pci_data *dev_gt_init(struct machine *machine, struct memory *mem,
220          uint64_t baseaddr, int irq_nr, int pciirq, int type)          uint64_t baseaddr, char *timer_irq_path, char *isa_irq_path, int type)
221  {  {
222          struct gt_data *d;          struct gt_data *d;
223          uint64_t pci_portbase = 0, pci_membase = 0;          uint64_t pci_portbase = 0, pci_membase = 0;
224          uint64_t isa_portbase = 0, isa_membase = 0;          uint64_t isa_portbase = 0, isa_membase = 0;
         int isa_irqbase = 0, pci_irqbase = 0;  
225          uint64_t pci_io_offset = 0, pci_mem_offset = 0;          uint64_t pci_io_offset = 0, pci_mem_offset = 0;
226          char *gt_name = "NO";          char *gt_name = "NO";
227    
228          d = malloc(sizeof(struct gt_data));          CHECK_ALLOCATION(d = malloc(sizeof(struct gt_data)));
         if (d == NULL) {  
                 fprintf(stderr, "out of memory\n");  
                 exit(1);  
         }  
229          memset(d, 0, sizeof(struct gt_data));          memset(d, 0, sizeof(struct gt_data));
230          d->timer0_irqnr = irq_nr;  
231            INTERRUPT_CONNECT(timer_irq_path, d->timer0_irq);
232    
233          switch (type) {          switch (type) {
234          case 11:          case 11:
# Line 244  struct pci_data *dev_gt_init(struct mach Line 239  struct pci_data *dev_gt_init(struct mach
239                  pci_mem_offset = 0;                  pci_mem_offset = 0;
240                  pci_portbase = 0x10000000ULL;                  pci_portbase = 0x10000000ULL;
241                  pci_membase = 0x10100000ULL;                  pci_membase = 0x10100000ULL;
                 pci_irqbase = 8;  
242                  isa_portbase = 0x10000000ULL;                  isa_portbase = 0x10000000ULL;
243                  isa_membase = 0x10100000ULL;                  isa_membase = 0x10100000ULL;
                 isa_irqbase = 8;  
244                  break;                  break;
245          case 120:          case 120:
246                  /*  EVBMIPS (Malta):  */                  /*  EVBMIPS (Malta):  */
# Line 257  struct pci_data *dev_gt_init(struct mach Line 250  struct pci_data *dev_gt_init(struct mach
250                  pci_mem_offset = 0;                  pci_mem_offset = 0;
251                  pci_portbase = 0x18000000ULL;                  pci_portbase = 0x18000000ULL;
252                  pci_membase = 0x10000000ULL;                  pci_membase = 0x10000000ULL;
                 pci_irqbase = 8;  
253                  isa_portbase = 0x18000000ULL;                  isa_portbase = 0x18000000ULL;
254                  isa_membase = 0x10000000ULL;                  isa_membase = 0x10000000ULL;
                 isa_irqbase = 8;  
255                  break;                  break;
256          case 260:          case 260:
257                  /*  MVMEPPC (mvme5500):  */                  /*  MVMEPPC (mvme5500):  */
# Line 270  struct pci_data *dev_gt_init(struct mach Line 261  struct pci_data *dev_gt_init(struct mach
261                  pci_mem_offset = 0;                  pci_mem_offset = 0;
262                  pci_portbase = 0x18000000ULL;                  pci_portbase = 0x18000000ULL;
263                  pci_membase = 0x10000000ULL;                  pci_membase = 0x10000000ULL;
                 pci_irqbase = 8;  
264                  isa_portbase = 0x18000000ULL;                  isa_portbase = 0x18000000ULL;
265                  isa_membase = 0x10000000ULL;                  isa_membase = 0x10000000ULL;
                 isa_irqbase = 8;  
266                  break;                  break;
267          default:fatal("dev_gt_init(): unimplemented GT type (%i).\n", type);          default:fatal("dev_gt_init(): unimplemented GT type (%i).\n", type);
268                  exit(1);                  exit(1);
269          }          }
270    
271    
         d->pci_irqbase = pci_irqbase;  
   
272          /*          /*
273           *  TODO: FIX THESE! Hardcoded numbers = bad.           *  TODO: FIX THESE! Hardcoded numbers = bad.
274           */           */
# Line 296  struct pci_data *dev_gt_init(struct mach Line 283  struct pci_data *dev_gt_init(struct mach
283          d->decode[GT_PCI0M1REMAP_OFS / 8] = d->decode[GT_PCI0M1LD_OFS / 8];          d->decode[GT_PCI0M1REMAP_OFS / 8] = d->decode[GT_PCI0M1LD_OFS / 8];
284    
285          d->pci_data = bus_pci_init(machine,          d->pci_data = bus_pci_init(machine,
286              pciirq, pci_io_offset, pci_mem_offset,              "TODO_gt_irq", pci_io_offset, pci_mem_offset,
287              pci_portbase, pci_membase, pci_irqbase,              pci_portbase, pci_membase, "TODO_pci_irqbase",
288              isa_portbase, isa_membase, isa_irqbase);              isa_portbase, isa_membase, isa_irq_path);
289    
290          /*          /*
291           *  According to NetBSD/cobalt:           *  According to NetBSD/cobalt:
# Line 309  struct pci_data *dev_gt_init(struct mach Line 296  struct pci_data *dev_gt_init(struct mach
296    
297          memory_device_register(mem, "gt", baseaddr, DEV_GT_LENGTH,          memory_device_register(mem, "gt", baseaddr, DEV_GT_LENGTH,
298              dev_gt_access, d, DM_DEFAULT, NULL);              dev_gt_access, d, DM_DEFAULT, NULL);
299          machine_add_tickfunction(machine, dev_gt_tick, d, TICK_SHIFT, 0.0);          machine_add_tickfunction(machine, dev_gt_tick, d, TICK_SHIFT);
300    
301          return d->pci_data;          return d->pci_data;
302  }  }
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