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/* |
/* |
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* Copyright (C) 2003-2006 Anders Gavare. All rights reserved. |
* Copyright (C) 2003-2007 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: dev_gt.c,v 1.40 2006/01/14 11:29:36 debug Exp $ |
* $Id: dev_gt.c,v 1.53 2007/06/16 05:09:55 debug Exp $ |
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* |
* |
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* Galileo Technology GT-64xxx PCI controller. |
* COMMENT: Galileo Technology GT-64xxx PCI controller |
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* |
* |
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* GT-64011 Used in Cobalt machines. |
* GT-64011 Used in Cobalt machines. |
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* GT-64120 Used in evbmips machines (Malta). |
* GT-64120 Used in evbmips machines (Malta). |
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* GT-64260 Used in mvmeppc machines. |
* GT-64260 Used in mvmeppc machines. |
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* |
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* TODO: This more or less just a dummy device, so far. It happens to work |
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* with some NetBSD ports in some cases, and perhaps with Linux too, |
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* but it is not really working for anything else. |
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*/ |
*/ |
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#include <stdio.h> |
#include <stdio.h> |
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#include "bus_pci.h" |
#include "bus_pci.h" |
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#include "cpu.h" |
#include "cpu.h" |
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#include "devices.h" |
#include "devices.h" |
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#include "interrupt.h" |
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#include "machine.h" |
#include "machine.h" |
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#include "memory.h" |
#include "memory.h" |
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#include "misc.h" |
#include "misc.h" |
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#include "timer.h" |
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#include "gtreg.h" |
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#define TICK_SHIFT 14 |
#define TICK_SHIFT 14 |
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#define PCI_PRODUCT_GALILEO_GT64120 0x4620 /* GT-64120 */ |
#define PCI_PRODUCT_GALILEO_GT64120 0x4620 /* GT-64120 */ |
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#define PCI_PRODUCT_GALILEO_GT64260 0x6430 /* GT-64260 */ |
#define PCI_PRODUCT_GALILEO_GT64260 0x6430 /* GT-64260 */ |
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struct gt_data { |
struct gt_data { |
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int irqnr; |
int type; |
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int pciirq; |
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int type; |
struct timer *timer; |
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struct interrupt timer0_irq; |
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int interrupt_hz; |
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int pending_timer0_interrupts; |
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/* Address decode registers: */ |
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uint32_t decode[GT_N_DECODE_REGS]; |
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struct pci_data *pci_data; |
struct pci_data *pci_data; |
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}; |
}; |
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/* |
/* |
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* dev_gt_tick(): |
* timer_tick(): |
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* |
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* Called d->interrupt_hz times per (real-world) second. |
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*/ |
*/ |
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void dev_gt_tick(struct cpu *cpu, void *extra) |
static void timer_tick(struct timer *timer, void *extra) |
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{ |
{ |
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struct gt_data *gt_data = extra; |
struct gt_data *d = extra; |
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d->pending_timer0_interrupts ++; |
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} |
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cpu_interrupt(cpu, gt_data->irqnr); |
DEVICE_TICK(gt) |
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{ |
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struct gt_data *d = extra; |
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if (d->pending_timer0_interrupts > 0) |
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INTERRUPT_ASSERT(d->timer0_irq); |
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} |
} |
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/* |
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* dev_gt_access(): |
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*/ |
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DEVICE_ACCESS(gt) |
DEVICE_ACCESS(gt) |
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{ |
{ |
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struct gt_data *d = extra; |
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uint64_t idata = 0, odata = 0; |
uint64_t idata = 0, odata = 0; |
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int bus, dev, func, reg; |
int bus, dev, func, reg; |
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size_t i; |
size_t i; |
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struct gt_data *d = extra; |
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if (writeflag == MEM_WRITE) |
if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len); |
idata = memory_readmax64(cpu, data, len); |
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switch (relative_addr) { |
switch (relative_addr) { |
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case 0x48: |
case GT_PCI0IOLD_OFS: |
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switch (d->type) { |
case GT_PCI0IOHD_OFS: |
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case PCI_PRODUCT_GALILEO_GT64120: |
case GT_PCI0M0LD_OFS: |
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/* |
case GT_PCI0M0HD_OFS: |
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* This is needed for Linux on Malta, according |
case GT_PCI0M1LD_OFS: |
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* to Alec Voropay. (TODO: Remove this hack when |
case GT_PCI0M1HD_OFS: |
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* things have stabilized.) |
case GT_PCI0IOREMAP_OFS: |
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*/ |
case GT_PCI0M0REMAP_OFS: |
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if (writeflag == MEM_READ) { |
case GT_PCI0M1REMAP_OFS: |
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odata = 0x18000000 >> 21; |
if (writeflag == MEM_READ) { |
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debug("[ gt: read from 0x48: 0x%08x ]\n", |
odata = d->decode[relative_addr / 8]; |
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(int)odata); |
debug("[ gt: read from offset 0x%x: 0x%x ]\n", |
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} |
(int)relative_addr, (int)odata); |
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break; |
} else { |
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default: |
d->decode[relative_addr / 8] = idata; |
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fatal("[ gt: access to 0x48? (type %i) ]\n", d->type); |
fatal("[ gt: write to offset 0x%x: 0x%x (TODO) ]\n", |
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(int)relative_addr, (int)idata); |
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} |
} |
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break; |
break; |
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case 0xc18: |
case GT_PCI0_CMD_OFS: |
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if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
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debug("[ gt: write to 0xc18: 0x%08x ]\n", (int)idata); |
debug("[ gt: write to GT_PCI0_CMD: 0x%08x (TODO) ]\n", |
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(int)idata); |
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} else { |
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debug("[ gt: read from GT_PCI0_CMD (0x%08x) (TODO) ]\n", |
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(int)odata); |
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} |
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break; |
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case GT_INTR_CAUSE: |
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if (writeflag == MEM_WRITE) { |
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debug("[ gt: write to GT_INTR_CAUSE: 0x%08x ]\n", |
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(int)idata); |
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return 1; |
return 1; |
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} else { |
} else { |
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odata = 0xffffffffULL; |
odata = GTIC_T0EXP; |
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/* |
INTERRUPT_DEASSERT(d->timer0_irq); |
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* ??? interrupt something... |
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* |
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* TODO: Remove this hack when things have stabilized. |
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*/ |
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odata = 0x00000100; |
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/* netbsd/cobalt cobalt/machdep.c:cpu_intr() */ |
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cpu_interrupt_ack(cpu, d->irqnr); |
if (d->pending_timer0_interrupts > 0) |
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d->pending_timer0_interrupts --; |
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debug("[ gt: read from 0xc18 (0x%08x) ]\n", (int)odata); |
debug("[ gt: read from GT_INTR_CAUSE (0x%08x) ]\n", |
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(int)odata); |
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} |
} |
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break; |
break; |
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case 0xc34: /* GT_PCI0_INTR_ACK */ |
case GT_PCI0_INTR_ACK: |
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odata = cpu->machine->isa_pic_data.last_int; |
odata = cpu->machine->isa_pic_data.last_int; |
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cpu_interrupt_ack(cpu, 8 + odata); |
/* TODO: Actually ack the interrupt? */ |
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break; |
break; |
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case 0xcf8: /* PCI ADDR */ |
case GT_TIMER_CTRL: |
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if (writeflag == MEM_WRITE) { |
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if (idata & ENTC0) { |
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/* TODO: Don't hardcode this. */ |
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d->interrupt_hz = 100; |
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if (d->timer == NULL) |
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d->timer = timer_add(d->interrupt_hz, |
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timer_tick, d); |
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else |
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timer_update_frequency(d->timer, |
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d->interrupt_hz); |
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} |
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} |
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break; |
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case GT_PCI0_CFG_ADDR: |
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if (cpu->byte_order != EMUL_LITTLE_ENDIAN) { |
if (cpu->byte_order != EMUL_LITTLE_ENDIAN) { |
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fatal("[ gt: TODO: big endian PCI access ]\n"); |
fatal("[ gt: TODO: big endian PCI access ]\n"); |
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exit(1); |
exit(1); |
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bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg); |
bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg); |
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break; |
break; |
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case 0xcfc: /* PCI DATA */ |
case GT_PCI0_CFG_DATA: |
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if (cpu->byte_order != EMUL_LITTLE_ENDIAN) { |
if (cpu->byte_order != EMUL_LITTLE_ENDIAN) { |
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fatal("[ gt: TODO: big endian PCI access ]\n"); |
fatal("[ gt: TODO: big endian PCI access ]\n"); |
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exit(1); |
exit(1); |
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/* |
/* |
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* dev_gt_init(): |
* dev_gt_init(): |
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* |
* |
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* Initialize a GT device. Return a pointer to the pci_data used, so that |
* Initialize a Gallileo PCI controller device. First, the controller itself |
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* the caller may add PCI devices. First, however, we add the GT device |
* is added to the bus, then a pointer to the bus is returned. |
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* itself. |
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*/ |
*/ |
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struct pci_data *dev_gt_init(struct machine *machine, struct memory *mem, |
struct pci_data *dev_gt_init(struct machine *machine, struct memory *mem, |
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uint64_t baseaddr, int irq_nr, int pciirq, int type) |
uint64_t baseaddr, char *timer_irq_path, char *isa_irq_path, int type) |
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{ |
{ |
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struct gt_data *d; |
struct gt_data *d; |
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uint64_t pci_portbase = 0, pci_membase = 0; |
uint64_t pci_portbase = 0, pci_membase = 0; |
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uint64_t isa_portbase = 0, isa_membase = 0; |
uint64_t isa_portbase = 0, isa_membase = 0; |
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int isa_irqbase = 0, pci_irqbase = 0; |
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uint64_t pci_io_offset = 0, pci_mem_offset = 0; |
uint64_t pci_io_offset = 0, pci_mem_offset = 0; |
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char *gt_name = "NO"; |
char *gt_name = "NO"; |
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d = malloc(sizeof(struct gt_data)); |
CHECK_ALLOCATION(d = malloc(sizeof(struct gt_data))); |
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if (d == NULL) { |
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fprintf(stderr, "out of memory\n"); |
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exit(1); |
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} |
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memset(d, 0, sizeof(struct gt_data)); |
memset(d, 0, sizeof(struct gt_data)); |
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d->irqnr = irq_nr; |
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d->pciirq = pciirq; |
INTERRUPT_CONNECT(timer_irq_path, d->timer0_irq); |
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switch (type) { |
switch (type) { |
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case 11: |
case 11: |
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pci_mem_offset = 0; |
pci_mem_offset = 0; |
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pci_portbase = 0x10000000ULL; |
pci_portbase = 0x10000000ULL; |
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pci_membase = 0x10100000ULL; |
pci_membase = 0x10100000ULL; |
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pci_irqbase = 0; |
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isa_portbase = 0x10000000ULL; |
isa_portbase = 0x10000000ULL; |
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isa_membase = 0x10100000ULL; |
isa_membase = 0x10100000ULL; |
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isa_irqbase = 8; |
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break; |
break; |
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case 120: |
case 120: |
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/* EVBMIPS (Malta): */ |
/* EVBMIPS (Malta): */ |
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pci_mem_offset = 0; |
pci_mem_offset = 0; |
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pci_portbase = 0x18000000ULL; |
pci_portbase = 0x18000000ULL; |
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pci_membase = 0x10000000ULL; |
pci_membase = 0x10000000ULL; |
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pci_irqbase = 8; |
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isa_portbase = 0x18000000ULL; |
isa_portbase = 0x18000000ULL; |
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isa_membase = 0x10000000ULL; |
isa_membase = 0x10000000ULL; |
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isa_irqbase = 8; |
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break; |
break; |
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case 260: |
case 260: |
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/* MVMEPPC (mvme5500): */ |
/* MVMEPPC (mvme5500): */ |
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pci_mem_offset = 0; |
pci_mem_offset = 0; |
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pci_portbase = 0x18000000ULL; |
pci_portbase = 0x18000000ULL; |
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pci_membase = 0x10000000ULL; |
pci_membase = 0x10000000ULL; |
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pci_irqbase = 8; |
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isa_portbase = 0x18000000ULL; |
isa_portbase = 0x18000000ULL; |
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isa_membase = 0x10000000ULL; |
isa_membase = 0x10000000ULL; |
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isa_irqbase = 8; |
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break; |
break; |
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default:fatal("dev_gt_init(): unimplemented GT type (%i).\n", type); |
default:fatal("dev_gt_init(): unimplemented GT type (%i).\n", type); |
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exit(1); |
exit(1); |
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} |
} |
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/* |
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* TODO: FIX THESE! Hardcoded numbers = bad. |
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*/ |
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d->decode[GT_PCI0IOLD_OFS / 8] = pci_portbase >> 21; |
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d->decode[GT_PCI0IOHD_OFS / 8] = 0x40; |
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d->decode[GT_PCI0M0LD_OFS / 8] = 0x80; |
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d->decode[GT_PCI0M0HD_OFS / 8] = 0x3f; |
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d->decode[GT_PCI0M1LD_OFS / 8] = 0xc1; |
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d->decode[GT_PCI0M1HD_OFS / 8] = 0x5e; |
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d->decode[GT_PCI0IOREMAP_OFS / 8] = d->decode[GT_PCI0IOLD_OFS / 8]; |
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d->decode[GT_PCI0M0REMAP_OFS / 8] = d->decode[GT_PCI0M0LD_OFS / 8]; |
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d->decode[GT_PCI0M1REMAP_OFS / 8] = d->decode[GT_PCI0M1LD_OFS / 8]; |
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d->pci_data = bus_pci_init(machine, |
d->pci_data = bus_pci_init(machine, |
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pciirq, pci_io_offset, pci_mem_offset, |
"TODO_gt_irq", pci_io_offset, pci_mem_offset, |
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pci_portbase, pci_membase, pci_irqbase, |
pci_portbase, pci_membase, "TODO_pci_irqbase", |
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isa_portbase, isa_membase, isa_irqbase); |
isa_portbase, isa_membase, isa_irq_path); |
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/* |
/* |
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* According to NetBSD/cobalt: |
* According to NetBSD/cobalt: |