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/* |
/* |
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* Copyright (C) 2003-2005 Anders Gavare. All rights reserved. |
* Copyright (C) 2003-2007 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: dev_gt.c,v 1.22 2005/06/20 08:19:58 debug Exp $ |
* $Id: dev_gt.c,v 1.53 2007/06/16 05:09:55 debug Exp $ |
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* |
* |
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* Galileo Technology GT-64xxx PCI controller. |
* COMMENT: Galileo Technology GT-64xxx PCI controller |
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* |
* |
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* GT-64011 Used in Cobalt machines. |
* GT-64011 Used in Cobalt machines. |
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* GT-64120 Used in evbmips machines (Malta). |
* GT-64120 Used in evbmips machines (Malta). |
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* |
* GT-64260 Used in mvmeppc machines. |
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* TODO: This more or less just a dummy device, so far. |
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*/ |
*/ |
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#include <stdio.h> |
#include <stdio.h> |
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#include "bus_pci.h" |
#include "bus_pci.h" |
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#include "cpu.h" |
#include "cpu.h" |
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#include "devices.h" |
#include "devices.h" |
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#include "interrupt.h" |
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#include "machine.h" |
#include "machine.h" |
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#include "memory.h" |
#include "memory.h" |
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#include "misc.h" |
#include "misc.h" |
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#include "timer.h" |
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#include "gtreg.h" |
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#define TICK_SHIFT 14 |
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#define TICK_STEPS_SHIFT 16 |
/* #define debug fatal */ |
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#define PCI_PRODUCT_GALILEO_GT64011 0x4146 /* GT-64011 */ |
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#define PCI_PRODUCT_GALILEO_GT64120 0x4620 /* GT-64120 */ |
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#define PCI_PRODUCT_GALILEO_GT64260 0x6430 /* GT-64260 */ |
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#define PCI_VENDOR_GALILEO 0x11ab /* Galileo Technology */ |
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#define PCI_PRODUCT_GALILEO_GT64011 0x4146 /* GT-64011 System Controller */ |
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#define PCI_PRODUCT_GALILEO_GT64120 0x4620 /* GT-64120 */ |
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struct gt_data { |
struct gt_data { |
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int reg[8]; |
int type; |
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int irqnr; |
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int pciirq; |
struct timer *timer; |
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int type; |
struct interrupt timer0_irq; |
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int interrupt_hz; |
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int pending_timer0_interrupts; |
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struct pci_data *pci_data; |
/* Address decode registers: */ |
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uint32_t decode[GT_N_DECODE_REGS]; |
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struct pci_data *pci_data; |
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}; |
}; |
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/* |
/* |
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* dev_gt_tick(): |
* timer_tick(): |
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* |
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* Called d->interrupt_hz times per (real-world) second. |
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*/ |
*/ |
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void dev_gt_tick(struct cpu *cpu, void *extra) |
static void timer_tick(struct timer *timer, void *extra) |
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{ |
{ |
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struct gt_data *gt_data = extra; |
struct gt_data *d = extra; |
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d->pending_timer0_interrupts ++; |
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} |
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cpu_interrupt(cpu, gt_data->irqnr); |
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DEVICE_TICK(gt) |
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{ |
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struct gt_data *d = extra; |
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if (d->pending_timer0_interrupts > 0) |
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INTERRUPT_ASSERT(d->timer0_irq); |
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} |
} |
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/* |
DEVICE_ACCESS(gt) |
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* dev_gt_access(): |
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*/ |
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int dev_gt_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr, |
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unsigned char *data, size_t len, int writeflag, void *extra) |
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{ |
{ |
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uint64_t idata = 0, odata = 0; |
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int i; |
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struct gt_data *d = extra; |
struct gt_data *d = extra; |
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uint64_t idata = 0, odata = 0; |
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int bus, dev, func, reg; |
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size_t i; |
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idata = memory_readmax64(cpu, data, len); |
if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len); |
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switch (relative_addr) { |
switch (relative_addr) { |
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case 0xc18: |
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case GT_PCI0IOLD_OFS: |
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case GT_PCI0IOHD_OFS: |
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case GT_PCI0M0LD_OFS: |
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case GT_PCI0M0HD_OFS: |
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case GT_PCI0M1LD_OFS: |
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case GT_PCI0M1HD_OFS: |
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case GT_PCI0IOREMAP_OFS: |
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case GT_PCI0M0REMAP_OFS: |
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case GT_PCI0M1REMAP_OFS: |
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if (writeflag == MEM_READ) { |
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odata = d->decode[relative_addr / 8]; |
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debug("[ gt: read from offset 0x%x: 0x%x ]\n", |
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(int)relative_addr, (int)odata); |
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} else { |
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d->decode[relative_addr / 8] = idata; |
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fatal("[ gt: write to offset 0x%x: 0x%x (TODO) ]\n", |
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(int)relative_addr, (int)idata); |
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} |
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break; |
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case GT_PCI0_CMD_OFS: |
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if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
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debug("[ gt write to 0xc18: data = 0x%08lx ]\n", |
debug("[ gt: write to GT_PCI0_CMD: 0x%08x (TODO) ]\n", |
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(long)idata); |
(int)idata); |
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return 1; |
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} else { |
} else { |
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odata = 0xffffffffULL; |
debug("[ gt: read from GT_PCI0_CMD (0x%08x) (TODO) ]\n", |
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/* ??? interrupt something... */ |
(int)odata); |
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} |
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break; |
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odata = 0x00000100; /* netbsd/cobalt cobalt/machdep.c:cpu_intr() */ |
case GT_INTR_CAUSE: |
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if (writeflag == MEM_WRITE) { |
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debug("[ gt: write to GT_INTR_CAUSE: 0x%08x ]\n", |
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(int)idata); |
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return 1; |
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} else { |
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odata = GTIC_T0EXP; |
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INTERRUPT_DEASSERT(d->timer0_irq); |
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cpu_interrupt_ack(cpu, d->irqnr); |
if (d->pending_timer0_interrupts > 0) |
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d->pending_timer0_interrupts --; |
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debug("[ gt read from 0xc18 (data = 0x%08lx) ]\n", |
debug("[ gt: read from GT_INTR_CAUSE (0x%08x) ]\n", |
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(long)odata); |
(int)odata); |
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} |
} |
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break; |
break; |
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case 0xcf8: /* PCI ADDR */ |
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case 0xcfc: /* PCI DATA */ |
case GT_PCI0_INTR_ACK: |
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odata = cpu->machine->isa_pic_data.last_int; |
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/* TODO: Actually ack the interrupt? */ |
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break; |
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case GT_TIMER_CTRL: |
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if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
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bus_pci_access(cpu, mem, relative_addr, &idata, |
if (idata & ENTC0) { |
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writeflag, d->pci_data); |
/* TODO: Don't hardcode this. */ |
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} else { |
d->interrupt_hz = 100; |
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bus_pci_access(cpu, mem, relative_addr, &odata, |
if (d->timer == NULL) |
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writeflag, d->pci_data); |
d->timer = timer_add(d->interrupt_hz, |
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timer_tick, d); |
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else |
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timer_update_frequency(d->timer, |
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d->interrupt_hz); |
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} |
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} |
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break; |
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case GT_PCI0_CFG_ADDR: |
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if (cpu->byte_order != EMUL_LITTLE_ENDIAN) { |
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fatal("[ gt: TODO: big endian PCI access ]\n"); |
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exit(1); |
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} |
} |
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bus_pci_decompose_1(idata, &bus, &dev, &func, ®); |
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bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg); |
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break; |
break; |
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case GT_PCI0_CFG_DATA: |
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if (cpu->byte_order != EMUL_LITTLE_ENDIAN) { |
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fatal("[ gt: TODO: big endian PCI access ]\n"); |
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exit(1); |
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} |
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bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ? |
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&odata : &idata, len, writeflag); |
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break; |
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default: |
default: |
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if (writeflag==MEM_READ) { |
if (writeflag == MEM_READ) { |
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debug("[ gt read from addr 0x%x ]\n", |
debug("[ gt: read from addr 0x%x ]\n", |
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(int)relative_addr); |
(int)relative_addr); |
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odata = d->reg[relative_addr]; |
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} else { |
} else { |
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debug("[ gt write to addr 0x%x:", (int)relative_addr); |
debug("[ gt: write to addr 0x%x:", (int)relative_addr); |
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for (i=0; i<len; i++) |
for (i=0; i<len; i++) |
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debug(" %02x", data[i]); |
debug(" %02x", data[i]); |
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debug(" ]\n"); |
debug(" ]\n"); |
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d->reg[relative_addr] = idata; |
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} |
} |
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} |
} |
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/* |
/* |
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* pci_gt_rr_011(): |
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*/ |
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static uint32_t pci_gt_rr_011(int reg) |
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{ |
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switch (reg) { |
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case 0x00: |
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return PCI_VENDOR_GALILEO + (PCI_PRODUCT_GALILEO_GT64011 << 16); |
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case 0x08: |
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return 0x06000001; /* Revision 1 */ |
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default: |
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return 0; |
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} |
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} |
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/* |
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* pci_gt_rr_120(): |
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*/ |
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static uint32_t pci_gt_rr_120(int reg) |
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{ |
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switch (reg) { |
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case 0x00: |
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return PCI_VENDOR_GALILEO + (PCI_PRODUCT_GALILEO_GT64120 << 16); |
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case 0x08: |
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return 0x06000002; /* Revision 2? */ |
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default: |
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return 0; |
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} |
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} |
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/* |
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* pci_gt_init(): |
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*/ |
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void pci_gt_init(struct machine *machine, struct memory *mem) |
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{ |
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} |
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/* |
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* dev_gt_init(): |
* dev_gt_init(): |
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* |
* |
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* Initialize a GT device. Return a pointer to the pci_data used, so that |
* Initialize a Gallileo PCI controller device. First, the controller itself |
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* the caller may add PCI devices. First, however, we add the GT device |
* is added to the bus, then a pointer to the bus is returned. |
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* itself. |
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*/ |
*/ |
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struct pci_data *dev_gt_init(struct machine *machine, struct memory *mem, |
struct pci_data *dev_gt_init(struct machine *machine, struct memory *mem, |
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uint64_t baseaddr, int irq_nr, int pciirq, int type) |
uint64_t baseaddr, char *timer_irq_path, char *isa_irq_path, int type) |
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{ |
{ |
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struct gt_data *d; |
struct gt_data *d; |
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uint64_t pci_portbase = 0, pci_membase = 0; |
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uint64_t isa_portbase = 0, isa_membase = 0; |
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uint64_t pci_io_offset = 0, pci_mem_offset = 0; |
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char *gt_name = "NO"; |
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d = malloc(sizeof(struct gt_data)); |
CHECK_ALLOCATION(d = malloc(sizeof(struct gt_data))); |
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if (d == NULL) { |
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fprintf(stderr, "out of memory\n"); |
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exit(1); |
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} |
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memset(d, 0, sizeof(struct gt_data)); |
memset(d, 0, sizeof(struct gt_data)); |
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d->irqnr = irq_nr; |
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d->pciirq = pciirq; |
INTERRUPT_CONNECT(timer_irq_path, d->timer0_irq); |
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d->pci_data = bus_pci_init(pciirq); |
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switch (type) { |
switch (type) { |
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case 11: |
case 11: |
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/* Cobalt: */ |
236 |
d->type = PCI_PRODUCT_GALILEO_GT64011; |
d->type = PCI_PRODUCT_GALILEO_GT64011; |
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gt_name = "gt64011"; |
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pci_io_offset = 0; |
239 |
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pci_mem_offset = 0; |
240 |
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pci_portbase = 0x10000000ULL; |
241 |
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pci_membase = 0x10100000ULL; |
242 |
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isa_portbase = 0x10000000ULL; |
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isa_membase = 0x10100000ULL; |
244 |
break; |
break; |
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case 120: |
case 120: |
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/* EVBMIPS (Malta): */ |
247 |
d->type = PCI_PRODUCT_GALILEO_GT64120; |
d->type = PCI_PRODUCT_GALILEO_GT64120; |
248 |
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gt_name = "gt64120"; |
249 |
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pci_io_offset = 0; |
250 |
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pci_mem_offset = 0; |
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pci_portbase = 0x18000000ULL; |
252 |
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pci_membase = 0x10000000ULL; |
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isa_portbase = 0x18000000ULL; |
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isa_membase = 0x10000000ULL; |
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break; |
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case 260: |
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/* MVMEPPC (mvme5500): */ |
258 |
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d->type = PCI_PRODUCT_GALILEO_GT64260; |
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gt_name = "gt64260"; |
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pci_io_offset = 0; |
261 |
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pci_mem_offset = 0; |
262 |
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pci_portbase = 0x18000000ULL; |
263 |
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pci_membase = 0x10000000ULL; |
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isa_portbase = 0x18000000ULL; |
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isa_membase = 0x10000000ULL; |
266 |
break; |
break; |
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default:fatal("dev_gt_init(): type must be 11 or 120.\n"); |
default:fatal("dev_gt_init(): unimplemented GT type (%i).\n", type); |
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exit(1); |
exit(1); |
269 |
} |
} |
270 |
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272 |
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/* |
273 |
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* TODO: FIX THESE! Hardcoded numbers = bad. |
274 |
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*/ |
275 |
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d->decode[GT_PCI0IOLD_OFS / 8] = pci_portbase >> 21; |
276 |
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d->decode[GT_PCI0IOHD_OFS / 8] = 0x40; |
277 |
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d->decode[GT_PCI0M0LD_OFS / 8] = 0x80; |
278 |
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d->decode[GT_PCI0M0HD_OFS / 8] = 0x3f; |
279 |
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d->decode[GT_PCI0M1LD_OFS / 8] = 0xc1; |
280 |
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d->decode[GT_PCI0M1HD_OFS / 8] = 0x5e; |
281 |
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d->decode[GT_PCI0IOREMAP_OFS / 8] = d->decode[GT_PCI0IOLD_OFS / 8]; |
282 |
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d->decode[GT_PCI0M0REMAP_OFS / 8] = d->decode[GT_PCI0M0LD_OFS / 8]; |
283 |
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d->decode[GT_PCI0M1REMAP_OFS / 8] = d->decode[GT_PCI0M1LD_OFS / 8]; |
284 |
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285 |
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d->pci_data = bus_pci_init(machine, |
286 |
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"TODO_gt_irq", pci_io_offset, pci_mem_offset, |
287 |
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pci_portbase, pci_membase, "TODO_pci_irqbase", |
288 |
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isa_portbase, isa_membase, isa_irq_path); |
289 |
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290 |
/* |
/* |
291 |
* According to NetBSD/cobalt: |
* According to NetBSD/cobalt: |
292 |
* pchb0 at pci0 dev 0 function 0: Galileo GT-64011 |
* pchb0 at pci0 dev 0 function 0: Galileo GT-64011 |
293 |
* System Controller, rev 1 |
* System Controller, rev 1 |
294 |
*/ |
*/ |
295 |
bus_pci_add(machine, d->pci_data, mem, 0, 0, 0, pci_gt_init, |
bus_pci_add(machine, d->pci_data, mem, 0, 0, 0, gt_name); |
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d->type == PCI_PRODUCT_GALILEO_GT64011? |
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pci_gt_rr_011 : pci_gt_rr_120); |
|
296 |
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297 |
memory_device_register(mem, "gt", baseaddr, DEV_GT_LENGTH, |
memory_device_register(mem, "gt", baseaddr, DEV_GT_LENGTH, |
298 |
dev_gt_access, d, MEM_DEFAULT, NULL); |
dev_gt_access, d, DM_DEFAULT, NULL); |
299 |
machine_add_tickfunction(machine, dev_gt_tick, d, TICK_STEPS_SHIFT); |
machine_add_tickfunction(machine, dev_gt_tick, d, TICK_SHIFT); |
300 |
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301 |
return d->pci_data; |
return d->pci_data; |
302 |
} |
} |