| 1 |
/* |
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* Copyright (C) 2005-2007 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 17 |
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: dev_footbridge.c,v 1.57 2007/06/15 19:11:15 debug Exp $ |
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* |
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* COMMENT: DC21285 "Footbridge" controller; used in Netwinder and Cats |
| 31 |
* |
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* TODO: |
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* o) Add actual support for the fcom serial port. |
| 34 |
* o) FIQs. |
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* o) Pretty much everything else as well :) (This entire thing |
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* is a quick hack to work primarily with NetBSD and OpenBSD |
| 37 |
* as guest OSes.) |
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*/ |
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|
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#include <stdio.h> |
| 41 |
#include <stdlib.h> |
| 42 |
#include <string.h> |
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|
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#include "bus_pci.h" |
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#include "console.h" |
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#include "cpu.h" |
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#include "device.h" |
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#include "devices.h" |
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#include "machine.h" |
| 50 |
#include "memory.h" |
| 51 |
#include "misc.h" |
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#include "timer.h" |
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|
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|
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#include "dc21285reg.h" |
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|
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#define DEV_FOOTBRIDGE_TICK_SHIFT 14 |
| 58 |
#define DEV_FOOTBRIDGE_LENGTH 0x400 |
| 59 |
|
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#define N_FOOTBRIDGE_TIMERS 4 |
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|
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struct footbridge_data { |
| 63 |
struct interrupt irq; |
| 64 |
|
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struct pci_data *pcibus; |
| 66 |
|
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int console_handle; |
| 68 |
|
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uint32_t timer_load[N_FOOTBRIDGE_TIMERS]; |
| 70 |
uint32_t timer_value[N_FOOTBRIDGE_TIMERS]; |
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uint32_t timer_control[N_FOOTBRIDGE_TIMERS]; |
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|
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struct interrupt timer_irq[N_FOOTBRIDGE_TIMERS]; |
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struct timer *timer[N_FOOTBRIDGE_TIMERS]; |
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int pending_timer_interrupts[N_FOOTBRIDGE_TIMERS]; |
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|
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int irq_asserted; |
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|
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uint32_t irq_status; |
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uint32_t irq_enable; |
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|
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uint32_t fiq_status; |
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uint32_t fiq_enable; |
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}; |
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|
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|
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static void timer_tick0(struct timer *t, void *extra) |
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{ ((struct footbridge_data *)extra)->pending_timer_interrupts[0] ++; } |
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static void timer_tick1(struct timer *t, void *extra) |
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{ ((struct footbridge_data *)extra)->pending_timer_interrupts[1] ++; } |
| 91 |
static void timer_tick2(struct timer *t, void *extra) |
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{ ((struct footbridge_data *)extra)->pending_timer_interrupts[2] ++; } |
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static void timer_tick3(struct timer *t, void *extra) |
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{ ((struct footbridge_data *)extra)->pending_timer_interrupts[3] ++; } |
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|
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|
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static void reload_timer_value(struct cpu *cpu, struct footbridge_data *d, |
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int timer_nr) |
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{ |
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double freq = (double)cpu->machine->emulated_hz; |
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int cycles = d->timer_load[timer_nr]; |
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|
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if (d->timer_control[timer_nr] & TIMER_FCLK_16) |
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cycles <<= 4; |
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else if (d->timer_control[timer_nr] & TIMER_FCLK_256) |
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cycles <<= 8; |
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freq /= (double)cycles; |
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|
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d->timer_value[timer_nr] = d->timer_load[timer_nr]; |
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|
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/* printf("%i: %i -> %f Hz\n", timer_nr, |
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d->timer_load[timer_nr], freq); */ |
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|
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if (d->timer[timer_nr] == NULL) { |
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switch (timer_nr) { |
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case 0: d->timer[0] = timer_add(freq, timer_tick0, d); break; |
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case 1: d->timer[1] = timer_add(freq, timer_tick1, d); break; |
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case 2: d->timer[2] = timer_add(freq, timer_tick2, d); break; |
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case 3: d->timer[3] = timer_add(freq, timer_tick3, d); break; |
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} |
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} else { |
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timer_update_frequency(d->timer[timer_nr], freq); |
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} |
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} |
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|
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|
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/* |
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* The 4 footbridge timers should decrease and cause interrupts. Periodic |
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* interrupts restart as soon as they are acknowledged, non-periodic |
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* interrupts need to be "reloaded" to restart. |
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* |
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* TODO: Hm. I thought I had solved this, but it didn't quite work. |
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* This needs to be re-checked against documentation, sometime. |
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*/ |
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DEVICE_TICK(footbridge) |
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{ |
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struct footbridge_data *d = extra; |
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int i; |
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|
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for (i=0; i<N_FOOTBRIDGE_TIMERS; i++) { |
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if (d->timer_control[i] & TIMER_ENABLE) { |
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if (d->pending_timer_interrupts[i] > 0) { |
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d->timer_value[i] = random() % d->timer_load[i]; |
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INTERRUPT_ASSERT(d->timer_irq[i]); |
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} |
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} |
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} |
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} |
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|
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|
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/* |
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* footbridge_interrupt_assert(): |
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*/ |
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void footbridge_interrupt_assert(struct interrupt *interrupt) |
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{ |
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struct footbridge_data *d = (struct footbridge_data *) interrupt->extra; |
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d->irq_status |= interrupt->line; |
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|
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if ((d->irq_status & d->irq_enable) && !d->irq_asserted) { |
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d->irq_asserted = 1; |
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INTERRUPT_ASSERT(d->irq); |
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} |
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} |
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|
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|
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/* |
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* footbridge_interrupt_deassert(): |
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*/ |
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void footbridge_interrupt_deassert(struct interrupt *interrupt) |
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{ |
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struct footbridge_data *d = (struct footbridge_data *) interrupt->extra; |
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d->irq_status &= ~interrupt->line; |
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|
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if (!(d->irq_status & d->irq_enable) && d->irq_asserted) { |
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d->irq_asserted = 0; |
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INTERRUPT_DEASSERT(d->irq); |
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} |
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} |
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|
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|
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/* |
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* Reading the byte at 0x79000000 is a quicker way to figure out which ISA |
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* interrupt has occurred (and acknowledging it at the same time), than |
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* dealing with the legacy 0x20/0xa0 ISA ports. |
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*/ |
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DEVICE_ACCESS(footbridge_isa) |
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{ |
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/* struct footbridge_data *d = extra; */ |
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uint64_t idata = 0, odata = 0; |
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int x; |
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|
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if (writeflag == MEM_WRITE) { |
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idata = memory_readmax64(cpu, data, len); |
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fatal("[ footbridge_isa: WARNING/TODO: write! ]\n"); |
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} |
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|
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x = cpu->machine->isa_pic_data.last_int; |
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if (x < 8) |
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odata = cpu->machine->isa_pic_data.pic1->irq_base + x; |
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else |
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odata = cpu->machine->isa_pic_data.pic2->irq_base + x - 8; |
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|
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if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len, odata); |
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|
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return 1; |
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} |
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|
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|
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/* |
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* Reset pin at ISA port 0x338, at least in the NetWinder: |
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* |
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* TODO: NOT WORKING YET! |
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*/ |
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DEVICE_ACCESS(footbridge_reset) |
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{ |
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uint64_t idata = 0; |
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|
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if (writeflag == MEM_WRITE) { |
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idata = memory_readmax64(cpu, data, len); |
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if (idata & 0x40) { |
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debug("[ footbridge_reset: GP16: Halting. ]\n"); |
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cpu->running = 0; |
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exit(1); |
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} |
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} |
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|
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return 1; |
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} |
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|
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|
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/* |
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* The Footbridge PCI configuration space is implemented as a direct memory |
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* space (i.e. not one port for addr and one port for data). This function |
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* translates that into bus_pci calls. |
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*/ |
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DEVICE_ACCESS(footbridge_pci) |
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{ |
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struct footbridge_data *d = extra; |
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uint64_t idata = 0, odata = 0; |
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int bus, dev, func, reg; |
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|
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if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN); |
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|
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/* Decompose the (direct) address into its components: */ |
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bus_pci_decompose_1(relative_addr, &bus, &dev, &func, ®); |
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bus_pci_setaddr(cpu, d->pcibus, bus, dev, func, reg); |
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|
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if (bus == 255) { |
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fatal("[ footbridge DEBUG ERROR: bus 255 unlikely," |
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" pc (might not be updated) = 0x%08x ]\n", (int)cpu->pc); |
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exit(1); |
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} |
| 255 |
|
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debug("[ footbridge pci: %s bus %i, device %i, function %i, register " |
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"%i ]\n", writeflag == MEM_READ? "read from" : "write to", bus, |
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dev, func, reg); |
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|
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bus_pci_data_access(cpu, d->pcibus, writeflag == MEM_READ? |
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&odata : &idata, len, writeflag); |
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|
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if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN, odata); |
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|
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return 1; |
| 267 |
} |
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|
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|
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DEVICE_ACCESS(footbridge) |
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{ |
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struct footbridge_data *d = extra; |
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uint64_t idata = 0, odata = 0; |
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int timer_nr = 0; |
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|
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if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len); |
| 278 |
|
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if (relative_addr >= TIMER_1_LOAD && relative_addr <= TIMER_4_CLEAR) { |
| 280 |
timer_nr = (relative_addr >> 5) & (N_FOOTBRIDGE_TIMERS - 1); |
| 281 |
relative_addr &= ~0x060; |
| 282 |
} |
| 283 |
|
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switch (relative_addr) { |
| 285 |
|
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case VENDOR_ID: |
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odata = 0x1011; /* DC21285_VENDOR_ID */ |
| 288 |
break; |
| 289 |
|
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case DEVICE_ID: |
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odata = 0x1065; /* DC21285_DEVICE_ID */ |
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break; |
| 293 |
|
| 294 |
case 0x04: |
| 295 |
case 0x0c: |
| 296 |
case 0x10: |
| 297 |
case 0x14: |
| 298 |
case 0x18: |
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/* TODO. Written to by Linux. */ |
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break; |
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|
| 302 |
case REVISION: |
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odata = 3; /* footbridge revision number */ |
| 304 |
break; |
| 305 |
|
| 306 |
case PCI_ADDRESS_EXTENSION: |
| 307 |
/* TODO: Written to by Linux. */ |
| 308 |
if (writeflag == MEM_WRITE && idata != 0) |
| 309 |
fatal("[ footbridge: TODO: write to PCI_ADDRESS_" |
| 310 |
"EXTENSION: 0x%llx ]\n", (long long)idata); |
| 311 |
break; |
| 312 |
|
| 313 |
case SA_CONTROL: |
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/* Read by Linux: */ |
| 315 |
odata = PCI_CENTRAL_FUNCTION; |
| 316 |
break; |
| 317 |
|
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case UART_DATA: |
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if (writeflag == MEM_WRITE) |
| 320 |
console_putchar(d->console_handle, idata); |
| 321 |
break; |
| 322 |
|
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case UART_RX_STAT: |
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/* TODO */ |
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odata = 0; |
| 326 |
break; |
| 327 |
|
| 328 |
case UART_FLAGS: |
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odata = UART_TX_EMPTY; |
| 330 |
break; |
| 331 |
|
| 332 |
case IRQ_STATUS: |
| 333 |
if (writeflag == MEM_READ) |
| 334 |
odata = d->irq_status & d->irq_enable; |
| 335 |
else { |
| 336 |
fatal("[ WARNING: footbridge write to irq status? ]\n"); |
| 337 |
exit(1); |
| 338 |
} |
| 339 |
break; |
| 340 |
|
| 341 |
case IRQ_RAW_STATUS: |
| 342 |
if (writeflag == MEM_READ) |
| 343 |
odata = d->irq_status; |
| 344 |
else { |
| 345 |
fatal("[ footbridge write to irq_raw_status ]\n"); |
| 346 |
exit(1); |
| 347 |
} |
| 348 |
break; |
| 349 |
|
| 350 |
case IRQ_ENABLE_SET: |
| 351 |
if (writeflag == MEM_WRITE) { |
| 352 |
d->irq_enable |= idata; |
| 353 |
if (d->irq_status & d->irq_enable) |
| 354 |
INTERRUPT_ASSERT(d->irq); |
| 355 |
else |
| 356 |
INTERRUPT_DEASSERT(d->irq); |
| 357 |
} else { |
| 358 |
odata = d->irq_enable; |
| 359 |
fatal("[ WARNING: footbridge read from " |
| 360 |
"ENABLE SET? ]\n"); |
| 361 |
exit(1); |
| 362 |
} |
| 363 |
break; |
| 364 |
|
| 365 |
case IRQ_ENABLE_CLEAR: |
| 366 |
if (writeflag == MEM_WRITE) { |
| 367 |
d->irq_enable &= ~idata; |
| 368 |
if (d->irq_status & d->irq_enable) |
| 369 |
INTERRUPT_ASSERT(d->irq); |
| 370 |
else |
| 371 |
INTERRUPT_DEASSERT(d->irq); |
| 372 |
} else { |
| 373 |
odata = d->irq_enable; |
| 374 |
fatal("[ WARNING: footbridge read from " |
| 375 |
"ENABLE CLEAR? ]\n"); |
| 376 |
exit(1); |
| 377 |
} |
| 378 |
break; |
| 379 |
|
| 380 |
case FIQ_STATUS: |
| 381 |
if (writeflag == MEM_READ) |
| 382 |
odata = d->fiq_status & d->fiq_enable; |
| 383 |
else { |
| 384 |
fatal("[ WARNING: footbridge write to fiq status? ]\n"); |
| 385 |
exit(1); |
| 386 |
} |
| 387 |
break; |
| 388 |
|
| 389 |
case FIQ_RAW_STATUS: |
| 390 |
if (writeflag == MEM_READ) |
| 391 |
odata = d->fiq_status; |
| 392 |
else { |
| 393 |
fatal("[ footbridge write to fiq_raw_status ]\n"); |
| 394 |
exit(1); |
| 395 |
} |
| 396 |
break; |
| 397 |
|
| 398 |
case FIQ_ENABLE_SET: |
| 399 |
if (writeflag == MEM_WRITE) |
| 400 |
d->fiq_enable |= idata; |
| 401 |
break; |
| 402 |
|
| 403 |
case FIQ_ENABLE_CLEAR: |
| 404 |
if (writeflag == MEM_WRITE) |
| 405 |
d->fiq_enable &= ~idata; |
| 406 |
break; |
| 407 |
|
| 408 |
case TIMER_1_LOAD: |
| 409 |
if (writeflag == MEM_READ) |
| 410 |
odata = d->timer_load[timer_nr]; |
| 411 |
else { |
| 412 |
d->timer_load[timer_nr] = idata & TIMER_MAX_VAL; |
| 413 |
reload_timer_value(cpu, d, timer_nr); |
| 414 |
/* debug("[ footbridge: timer %i (1-based), " |
| 415 |
"value %i ]\n", timer_nr + 1, |
| 416 |
(int)d->timer_value[timer_nr]); */ |
| 417 |
INTERRUPT_DEASSERT(d->timer_irq[timer_nr]); |
| 418 |
} |
| 419 |
break; |
| 420 |
|
| 421 |
case TIMER_1_VALUE: |
| 422 |
if (writeflag == MEM_READ) |
| 423 |
odata = d->timer_value[timer_nr]; |
| 424 |
else |
| 425 |
d->timer_value[timer_nr] = idata & TIMER_MAX_VAL; |
| 426 |
break; |
| 427 |
|
| 428 |
case TIMER_1_CONTROL: |
| 429 |
if (writeflag == MEM_READ) |
| 430 |
odata = d->timer_control[timer_nr]; |
| 431 |
else { |
| 432 |
d->timer_control[timer_nr] = idata; |
| 433 |
if (idata & TIMER_FCLK_16 && |
| 434 |
idata & TIMER_FCLK_256) { |
| 435 |
fatal("TODO: footbridge timer: " |
| 436 |
"both 16 and 256?\n"); |
| 437 |
exit(1); |
| 438 |
} |
| 439 |
if (idata & TIMER_ENABLE) { |
| 440 |
reload_timer_value(cpu, d, timer_nr); |
| 441 |
} else { |
| 442 |
d->pending_timer_interrupts[timer_nr] = 0; |
| 443 |
} |
| 444 |
INTERRUPT_DEASSERT(d->timer_irq[timer_nr]); |
| 445 |
} |
| 446 |
break; |
| 447 |
|
| 448 |
case TIMER_1_CLEAR: |
| 449 |
if (d->timer_control[timer_nr] & TIMER_MODE_PERIODIC) { |
| 450 |
reload_timer_value(cpu, d, timer_nr); |
| 451 |
} |
| 452 |
|
| 453 |
if (d->pending_timer_interrupts[timer_nr] > 0) { |
| 454 |
d->pending_timer_interrupts[timer_nr] --; |
| 455 |
} |
| 456 |
|
| 457 |
INTERRUPT_DEASSERT(d->timer_irq[timer_nr]); |
| 458 |
break; |
| 459 |
|
| 460 |
default:if (writeflag == MEM_READ) { |
| 461 |
fatal("[ footbridge: read from 0x%x ]\n", |
| 462 |
(int)relative_addr); |
| 463 |
} else { |
| 464 |
fatal("[ footbridge: write to 0x%x: 0x%llx ]\n", |
| 465 |
(int)relative_addr, (long long)idata); |
| 466 |
} |
| 467 |
} |
| 468 |
|
| 469 |
if (writeflag == MEM_READ) |
| 470 |
memory_writemax64(cpu, data, len, odata); |
| 471 |
|
| 472 |
return 1; |
| 473 |
} |
| 474 |
|
| 475 |
|
| 476 |
DEVINIT(footbridge) |
| 477 |
{ |
| 478 |
struct footbridge_data *d; |
| 479 |
char irq_path[300], irq_path_isa[300]; |
| 480 |
uint64_t pci_addr = 0x7b000000; |
| 481 |
int i; |
| 482 |
|
| 483 |
CHECK_ALLOCATION(d = malloc(sizeof(struct footbridge_data))); |
| 484 |
memset(d, 0, sizeof(struct footbridge_data)); |
| 485 |
|
| 486 |
/* Connect to the CPU which this footbridge will interrupt: */ |
| 487 |
INTERRUPT_CONNECT(devinit->interrupt_path, d->irq); |
| 488 |
|
| 489 |
/* DC21285 register access: */ |
| 490 |
memory_device_register(devinit->machine->memory, devinit->name, |
| 491 |
devinit->addr, DEV_FOOTBRIDGE_LENGTH, |
| 492 |
dev_footbridge_access, d, DM_DEFAULT, NULL); |
| 493 |
|
| 494 |
/* ISA interrupt status/acknowledgement: */ |
| 495 |
memory_device_register(devinit->machine->memory, "footbridge_isa", |
| 496 |
0x79000000, 8, dev_footbridge_isa_access, d, DM_DEFAULT, NULL); |
| 497 |
|
| 498 |
/* The "fcom" console: */ |
| 499 |
d->console_handle = console_start_slave(devinit->machine, "fcom", 0); |
| 500 |
|
| 501 |
/* Register 32 footbridge interrupts: */ |
| 502 |
snprintf(irq_path, sizeof(irq_path), "%s.footbridge", |
| 503 |
devinit->interrupt_path); |
| 504 |
for (i=0; i<32; i++) { |
| 505 |
struct interrupt interrupt_template; |
| 506 |
char tmpstr[200]; |
| 507 |
|
| 508 |
memset(&interrupt_template, 0, sizeof(interrupt_template)); |
| 509 |
interrupt_template.line = 1 << i; |
| 510 |
snprintf(tmpstr, sizeof(tmpstr), "%s.%i", irq_path, i); |
| 511 |
interrupt_template.name = tmpstr; |
| 512 |
|
| 513 |
interrupt_template.extra = d; |
| 514 |
interrupt_template.interrupt_assert = |
| 515 |
footbridge_interrupt_assert; |
| 516 |
interrupt_template.interrupt_deassert = |
| 517 |
footbridge_interrupt_deassert; |
| 518 |
interrupt_handler_register(&interrupt_template); |
| 519 |
|
| 520 |
/* Connect locally to some interrupts: */ |
| 521 |
if (i>=IRQ_TIMER_1 && i<=IRQ_TIMER_4) |
| 522 |
INTERRUPT_CONNECT(tmpstr, d->timer_irq[i-IRQ_TIMER_1]); |
| 523 |
} |
| 524 |
|
| 525 |
switch (devinit->machine->machine_type) { |
| 526 |
case MACHINE_CATS: |
| 527 |
snprintf(irq_path_isa, sizeof(irq_path_isa), "%s.10", irq_path); |
| 528 |
break; |
| 529 |
case MACHINE_NETWINDER: |
| 530 |
snprintf(irq_path_isa, sizeof(irq_path_isa), "%s.11", irq_path); |
| 531 |
break; |
| 532 |
default:fatal("footbridge unimpl machine type\n"); |
| 533 |
exit(1); |
| 534 |
} |
| 535 |
|
| 536 |
/* A PCI bus: */ |
| 537 |
d->pcibus = bus_pci_init( |
| 538 |
devinit->machine, |
| 539 |
irq_path, |
| 540 |
0x7c000000, /* PCI device io offset */ |
| 541 |
0x80000000, /* PCI device mem offset */ |
| 542 |
0x00000000, /* PCI port base */ |
| 543 |
0x00000000, /* PCI mem base */ |
| 544 |
irq_path, /* PCI irq base */ |
| 545 |
0x7c000000, /* ISA port base */ |
| 546 |
0x80000000, /* ISA mem base */ |
| 547 |
irq_path_isa); /* ISA port base */ |
| 548 |
|
| 549 |
/* ... with some default devices for known machine types: */ |
| 550 |
switch (devinit->machine->machine_type) { |
| 551 |
case MACHINE_CATS: |
| 552 |
bus_pci_add(devinit->machine, d->pcibus, |
| 553 |
devinit->machine->memory, 0xc0, 7, 0, "ali_m1543"); |
| 554 |
bus_pci_add(devinit->machine, d->pcibus, |
| 555 |
devinit->machine->memory, 0xc0, 10, 0, "dec21143"); |
| 556 |
bus_pci_add(devinit->machine, d->pcibus, |
| 557 |
devinit->machine->memory, 0xc0, 16, 0, "ali_m5229"); |
| 558 |
break; |
| 559 |
case MACHINE_NETWINDER: |
| 560 |
bus_pci_add(devinit->machine, d->pcibus, |
| 561 |
devinit->machine->memory, 0xc0, 11, 0, "symphony_83c553"); |
| 562 |
bus_pci_add(devinit->machine, d->pcibus, |
| 563 |
devinit->machine->memory, 0xc0, 11, 1, "symphony_82c105"); |
| 564 |
memory_device_register(devinit->machine->memory, |
| 565 |
"footbridge_reset", 0x7c000338, 1, |
| 566 |
dev_footbridge_reset_access, d, DM_DEFAULT, NULL); |
| 567 |
break; |
| 568 |
default:fatal("footbridge: unimplemented machine type.\n"); |
| 569 |
exit(1); |
| 570 |
} |
| 571 |
|
| 572 |
/* PCI configuration space: */ |
| 573 |
memory_device_register(devinit->machine->memory, |
| 574 |
"footbridge_pci", pci_addr, 0x1000000, |
| 575 |
dev_footbridge_pci_access, d, DM_DEFAULT, NULL); |
| 576 |
|
| 577 |
/* Timer ticks: */ |
| 578 |
for (i=0; i<N_FOOTBRIDGE_TIMERS; i++) { |
| 579 |
d->timer_control[i] = TIMER_MODE_PERIODIC; |
| 580 |
d->timer_load[i] = TIMER_MAX_VAL; |
| 581 |
} |
| 582 |
|
| 583 |
machine_add_tickfunction(devinit->machine, |
| 584 |
dev_footbridge_tick, d, DEV_FOOTBRIDGE_TICK_SHIFT); |
| 585 |
|
| 586 |
devinit->return_ptr = d->pcibus; |
| 587 |
return 1; |
| 588 |
} |
| 589 |
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