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dpavlin |
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/* |
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dpavlin |
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* Copyright (C) 2003-2007 Anders Gavare. All rights reserved. |
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dpavlin |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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dpavlin |
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* $Id: dev_dec5800.c,v 1.23 2007/06/15 18:44:19 debug Exp $ |
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* |
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* COMMENT: DECsystem 58x0 devices |
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* |
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dpavlin |
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* Emulation of devices found in a DECsystem 58x0, where x is the number |
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* of CPUs in the system. (The CPU board is called KN5800 by Ultrix.) |
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* |
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* o) timers and misc stuff |
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* o) BI (Backplane Interconnect) |
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* o) CCA (Console Communication Area) |
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* o) XMI (Extended Memory Interconnect) |
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* |
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* TODO: This hardware is not very easy to find docs about. |
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* Perhaps VAX 6000/300 docs? |
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*/ |
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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#include "console.h" |
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#include "cpu.h" |
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dpavlin |
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#include "device.h" |
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dpavlin |
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#include "devices.h" |
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dpavlin |
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#include "interrupt.h" |
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dpavlin |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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dpavlin |
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#define DEV_DEC5800_LENGTH 0x1000 /* TODO */ |
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struct dec5800_data { |
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uint32_t csr; |
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struct interrupt cpu_irq; |
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uint32_t vector_0x50; |
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struct interrupt timer_irq; |
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}; |
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void dec5800_interrupt_assert(struct interrupt *interrupt) |
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dpavlin |
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{ |
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dpavlin |
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struct dec5800_data *d = interrupt->extra; |
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d->csr |= (1 << interrupt->line); |
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if (d->csr & 0x10000000) |
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INTERRUPT_ASSERT(d->cpu_irq); |
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} |
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void dec5800_interrupt_deassert(struct interrupt *interrupt) |
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{ |
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struct dec5800_data *d = interrupt->extra; |
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d->csr &= ~(1 << interrupt->line); |
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if (!(d->csr & 0x10000000)) |
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INTERRUPT_DEASSERT(d->cpu_irq); |
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} |
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DEVICE_TICK(dec5800) |
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{ |
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dpavlin |
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struct dec5800_data *d = extra; |
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/* Timer interrupts? */ |
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if (d->csr & 0x8000) { |
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debug("[ dec5800: timer interrupt! ]\n"); |
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/* Set timer interrupt pending bit: */ |
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d->csr |= 0x20000000; |
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dpavlin |
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INTERRUPT_ASSERT(d->timer_irq); |
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dpavlin |
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} |
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} |
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dpavlin |
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DEVICE_ACCESS(dec5800_vectors) |
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dpavlin |
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{ |
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uint64_t idata = 0, odata = 0; |
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struct dec5800_data *d = extra; |
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dpavlin |
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if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len); |
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dpavlin |
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if (writeflag == MEM_READ) { |
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/* TODO */ |
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/* 0xfc = transmit interrupt, 0xf8 = receive interrupt, |
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0x80 = IPI */ |
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odata = d->vector_0x50; |
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/* odata = 0xfc; */ |
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debug("[ dec5800_vectors: read from 0x%02x: 0x%02x ]\n", |
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(int)relative_addr, (int)odata); |
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} else { |
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d->vector_0x50 = idata; |
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debug("[ dec5800_vectors: write to 0x%02x: 0x%02x ]\n", |
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(int)relative_addr, (int)idata); |
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} |
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if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len, odata); |
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return 1; |
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} |
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dpavlin |
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DEVICE_ACCESS(dec5800) |
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dpavlin |
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{ |
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uint64_t idata = 0, odata = 0; |
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struct dec5800_data *d = extra; |
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dpavlin |
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if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len); |
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dpavlin |
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/* Lowest 4 bits of csr contain cpu id: */ |
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d->csr = (d->csr & ~0xf) | (cpu->cpu_id & 0xf); |
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switch (relative_addr) { |
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case 0x0000: /* csr */ |
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if (writeflag == MEM_READ) { |
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odata = d->csr; |
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odata ^= random() & 0x10000; |
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debug("[ dec5800: read from csr: 0x%08x ]\n", |
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(int)odata); |
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} else { |
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d->csr = idata; |
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/* Ack. timer interrupts: */ |
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d->csr &= ~0x20000000; |
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dpavlin |
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INTERRUPT_DEASSERT(d->timer_irq); |
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dpavlin |
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debug("[ dec5800: write to csr: 0x%08x ]\n", |
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(int)idata); |
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} |
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break; |
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default: |
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if (writeflag==MEM_READ) { |
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debug("[ dec5800: read from 0x%08lx ]\n", |
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(long)relative_addr); |
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} else { |
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debug("[ dec5800: write to 0x%08lx: 0x%08x ]\n", |
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(long)relative_addr, (int)idata); |
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} |
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} |
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if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len, odata); |
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return 1; |
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} |
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dpavlin |
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DEVINIT(dec5800) |
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dpavlin |
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{ |
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struct dec5800_data *d; |
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dpavlin |
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char tmpstr[200]; |
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int i; |
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dpavlin |
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dpavlin |
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CHECK_ALLOCATION(d = malloc(sizeof(struct dec5800_data))); |
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dpavlin |
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memset(d, 0, sizeof(struct dec5800_data)); |
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dpavlin |
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snprintf(tmpstr, sizeof(tmpstr), "%s.2", devinit->interrupt_path); |
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INTERRUPT_CONNECT(tmpstr, d->cpu_irq); |
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snprintf(tmpstr, sizeof(tmpstr), "%s.3", devinit->interrupt_path); |
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INTERRUPT_CONNECT(tmpstr, d->timer_irq); |
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/* Register 32 CSR interrupts, corresponding to bits in the CSR: */ |
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for (i=0; i<32; i++) { |
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char n[200]; |
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struct interrupt template; |
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snprintf(n, sizeof(n), "%s.dec5800.%i", |
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devinit->interrupt_path, i); |
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memset(&template, 0, sizeof(template)); |
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template.line = i; |
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template.name = n; |
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template.extra = d; |
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template.interrupt_assert = dec5800_interrupt_assert; |
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template.interrupt_deassert = dec5800_interrupt_deassert; |
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interrupt_handler_register(&template); |
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} |
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memory_device_register(devinit->machine->memory, "dec5800", |
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devinit->addr, DEV_DEC5800_LENGTH, dev_dec5800_access, |
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dpavlin |
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d, DM_DEFAULT, NULL); |
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dpavlin |
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memory_device_register(devinit->machine->memory, "dec5800_vectors", |
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devinit->addr + 0x30000000, 0x100, dev_dec5800_vectors_access, |
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d, DM_DEFAULT, NULL); |
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machine_add_tickfunction(devinit->machine, dev_dec5800_tick, |
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dpavlin |
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d, 14); |
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dpavlin |
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dpavlin |
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return 1; |
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dpavlin |
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} |
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/*****************************************************************************/ |
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#include "bireg.h" |
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dpavlin |
34 |
/* 16 slots, 0x2000 bytes each */ |
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#define DEV_DECBI_LENGTH 0x20000 |
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dpavlin |
4 |
struct decbi_data { |
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int csr[NNODEBI]; |
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}; |
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dpavlin |
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DEVICE_ACCESS(decbi) |
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dpavlin |
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{ |
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uint64_t idata = 0, odata = 0; |
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int node_nr; |
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struct decbi_data *d = extra; |
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dpavlin |
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if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len); |
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dpavlin |
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relative_addr += BI_NODESIZE; /* HACK */ |
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node_nr = relative_addr / BI_NODESIZE; |
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relative_addr &= (BI_NODESIZE - 1); |
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/* TODO: This "1" here is the max node number in actual use. */ |
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if (node_nr > 1 || node_nr >= NNODEBI) |
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return 0; |
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switch (relative_addr) { |
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case BIREG_DTYPE: |
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if (writeflag==MEM_READ) { |
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/* |
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* This is a list of the devices in our BI slots: |
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*/ |
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switch (node_nr) { |
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case 1: odata = BIDT_KDB50; break; /* Disk */ |
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/* case 2: odata = BIDT_DEBNA; break; */ |
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/* BIDT_DEBNA = Ethernet */ |
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/* case 3: odata = BIDT_MS820; break; */ |
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/* BIDT_MS820 = Memory */ |
263 |
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default: |
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/* No device. */ |
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odata = 0; |
266 |
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} |
267 |
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debug("[ decbi: (node %i) read from BIREG_DTYPE:" |
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" 0x%x ]\n", node_nr, (int)odata); |
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} else { |
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debug("[ decbi: (node %i) attempt to write to " |
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"BIREG_DTYPE: 0x%08x ]\n", node_nr, (int)idata); |
273 |
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} |
274 |
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break; |
275 |
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case BIREG_VAXBICSR: |
276 |
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if (writeflag==MEM_READ) { |
277 |
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odata = (d->csr[node_nr] & ~BICSR_NODEMASK) | node_nr; |
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debug("[ decbi: (node %i) read from BIREG_" |
279 |
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"VAXBICSR: 0x%x ]\n", node_nr, (int)odata); |
280 |
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} else { |
281 |
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d->csr[node_nr] = idata; |
282 |
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debug("[ decbi: (node %i) attempt to write to " |
283 |
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"BIREG_VAXBICSR: 0x%08x ]\n", node_nr, (int)idata); |
284 |
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} |
285 |
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break; |
286 |
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case 0xf4: |
287 |
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if (writeflag==MEM_READ) { |
288 |
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odata = 0xffff; /* ? */ |
289 |
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debug("[ decbi: (node %i) read from 0xf4: " |
290 |
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"0x%x ]\n", node_nr, (int)odata); |
291 |
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} else { |
292 |
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debug("[ decbi: (node %i) attempt to write " |
293 |
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"to 0xf4: 0x%08x ]\n", node_nr, (int)idata); |
294 |
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} |
295 |
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break; |
296 |
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default: |
297 |
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if (writeflag==MEM_READ) { |
298 |
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debug("[ decbi: (node %i) read from unimplemented " |
299 |
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"0x%08lx ]\n", node_nr, (long)relative_addr, |
300 |
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(int)odata); |
301 |
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} else { |
302 |
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debug("[ decbi: (node %i) write to unimplemented " |
303 |
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"0x%08lx: 0x%08x ]\n", node_nr, |
304 |
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(long)relative_addr, (int)idata); |
305 |
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} |
306 |
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} |
307 |
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308 |
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if (writeflag == MEM_READ) |
309 |
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memory_writemax64(cpu, data, len, odata); |
310 |
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311 |
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return 1; |
312 |
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} |
313 |
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314 |
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315 |
dpavlin |
34 |
DEVINIT(decbi) |
316 |
dpavlin |
4 |
{ |
317 |
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struct decbi_data *d; |
318 |
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319 |
dpavlin |
42 |
CHECK_ALLOCATION(d = malloc(sizeof(struct decbi_data))); |
320 |
dpavlin |
4 |
memset(d, 0, sizeof(struct decbi_data)); |
321 |
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322 |
dpavlin |
34 |
memory_device_register(devinit->machine->memory, "decbi", |
323 |
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devinit->addr + 0x2000, DEV_DECBI_LENGTH - 0x2000, |
324 |
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dev_decbi_access, d, DM_DEFAULT, NULL); |
325 |
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326 |
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return 1; |
327 |
dpavlin |
4 |
} |
328 |
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329 |
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330 |
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/*****************************************************************************/ |
331 |
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332 |
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333 |
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/* |
334 |
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* CCA, "Console Communication Area" for a DEC 5800 SMP system. |
335 |
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*/ |
336 |
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337 |
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struct deccca_data { |
338 |
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int dummy; |
339 |
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}; |
340 |
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341 |
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342 |
dpavlin |
22 |
DEVICE_ACCESS(deccca) |
343 |
dpavlin |
4 |
{ |
344 |
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uint64_t idata = 0, odata = 0; |
345 |
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/* struct deccca_data *d = extra; */ |
346 |
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347 |
dpavlin |
18 |
if (writeflag == MEM_WRITE) |
348 |
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idata = memory_readmax64(cpu, data, len); |
349 |
dpavlin |
4 |
|
350 |
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switch (relative_addr) { |
351 |
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case 6: |
352 |
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case 7: |
353 |
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/* CCA "ID" bytes? These must be here, or Ultrix complains. */ |
354 |
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if (writeflag == MEM_READ) |
355 |
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odata = 67; |
356 |
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break; |
357 |
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case 8: |
358 |
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if (writeflag == MEM_READ) |
359 |
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odata = cpu->machine->ncpus; |
360 |
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break; |
361 |
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case 20: |
362 |
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if (writeflag == MEM_READ) |
363 |
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odata = (1 << cpu->machine->ncpus) - 1; |
364 |
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/* one bit for each cpu */ |
365 |
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break; |
366 |
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case 28: |
367 |
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if (writeflag == MEM_READ) |
368 |
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odata = (1 << cpu->machine->ncpus) - 1; |
369 |
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/* one bit for each enabled(?) cpu */ |
370 |
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break; |
371 |
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default: |
372 |
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if (writeflag==MEM_READ) { |
373 |
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debug("[ deccca: read from 0x%08lx ]\n", |
374 |
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(long)relative_addr); |
375 |
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} else { |
376 |
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debug("[ deccca: write to 0x%08lx: 0x%08x ]\n", |
377 |
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(long)relative_addr, (int)idata); |
378 |
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} |
379 |
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} |
380 |
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381 |
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|
if (writeflag == MEM_READ) |
382 |
|
|
memory_writemax64(cpu, data, len, odata); |
383 |
|
|
|
384 |
|
|
return 1; |
385 |
|
|
} |
386 |
|
|
|
387 |
|
|
|
388 |
|
|
/* |
389 |
|
|
* dev_deccca_init(): |
390 |
|
|
*/ |
391 |
|
|
void dev_deccca_init(struct memory *mem, uint64_t baseaddr) |
392 |
|
|
{ |
393 |
|
|
struct deccca_data *d; |
394 |
|
|
|
395 |
dpavlin |
42 |
CHECK_ALLOCATION(d = malloc(sizeof(struct deccca_data))); |
396 |
dpavlin |
4 |
memset(d, 0, sizeof(struct deccca_data)); |
397 |
|
|
|
398 |
|
|
memory_device_register(mem, "deccca", baseaddr, DEV_DECCCA_LENGTH, |
399 |
dpavlin |
20 |
dev_deccca_access, d, DM_DEFAULT, NULL); |
400 |
dpavlin |
4 |
} |
401 |
|
|
|
402 |
|
|
|
403 |
|
|
/*****************************************************************************/ |
404 |
|
|
|
405 |
|
|
|
406 |
|
|
/* |
407 |
|
|
* DEC 5800 XMI (this has to do with SMP...) |
408 |
|
|
*/ |
409 |
|
|
|
410 |
|
|
#include "xmireg.h" |
411 |
|
|
|
412 |
|
|
struct decxmi_data { |
413 |
|
|
uint32_t reg_0xc[NNODEXMI]; |
414 |
|
|
}; |
415 |
|
|
|
416 |
|
|
|
417 |
|
|
/* |
418 |
|
|
* dev_decxmi_access(): |
419 |
|
|
*/ |
420 |
dpavlin |
22 |
DEVICE_ACCESS(decxmi) |
421 |
dpavlin |
4 |
{ |
422 |
|
|
uint64_t idata = 0, odata = 0; |
423 |
|
|
int node_nr; |
424 |
|
|
struct decxmi_data *d = extra; |
425 |
|
|
|
426 |
dpavlin |
18 |
if (writeflag == MEM_WRITE) |
427 |
|
|
idata = memory_readmax64(cpu, data, len); |
428 |
dpavlin |
4 |
|
429 |
|
|
node_nr = relative_addr / XMI_NODESIZE; |
430 |
|
|
relative_addr &= (XMI_NODESIZE - 1); |
431 |
|
|
|
432 |
|
|
if (node_nr >= cpu->machine->ncpus + 1 || node_nr >= NNODEXMI) |
433 |
|
|
return 0; |
434 |
|
|
|
435 |
|
|
switch (relative_addr) { |
436 |
|
|
case XMI_TYPE: |
437 |
|
|
if (writeflag == MEM_READ) { |
438 |
|
|
/* |
439 |
|
|
* The first node is an XMI->BI adapter node, and then |
440 |
|
|
* there are n CPU nodes. |
441 |
|
|
*/ |
442 |
|
|
odata = XMIDT_ISIS; |
443 |
|
|
if (node_nr == 0) |
444 |
|
|
odata = XMIDT_DWMBA; |
445 |
|
|
|
446 |
|
|
debug("[ decxmi: (node %i) read from XMI_TYPE: " |
447 |
|
|
"0x%08x ]\n", node_nr, (int)odata); |
448 |
|
|
} else |
449 |
|
|
debug("[ decxmi: (node %i) write to XMI_TYPE: " |
450 |
|
|
"0x%08x ]\n", node_nr, (int)idata); |
451 |
|
|
break; |
452 |
|
|
case XMI_BUSERR: |
453 |
|
|
if (writeflag == MEM_READ) { |
454 |
|
|
odata = 0; |
455 |
|
|
debug("[ decxmi: (node %i) read from XMI_BUSERR: " |
456 |
|
|
"0x%08x ]\n", node_nr, (int)odata); |
457 |
|
|
} else |
458 |
|
|
debug("[ decxmi: (node %i) write to XMI_BUSERR: " |
459 |
|
|
"0x%08x ]\n", node_nr, (int)idata); |
460 |
|
|
break; |
461 |
|
|
case XMI_FAIL: |
462 |
|
|
if (writeflag == MEM_READ) { |
463 |
|
|
odata = 0; |
464 |
|
|
debug("[ decxmi: (node %i) read from XMI_FAIL: " |
465 |
|
|
"0x%08x ]\n", node_nr, (int)odata); |
466 |
|
|
} else |
467 |
|
|
debug("[ decxmi: (node %i) write to XMI_FAIL: " |
468 |
|
|
"0x%08x ]\n", node_nr, (int)idata); |
469 |
|
|
break; |
470 |
|
|
case 0xc: |
471 |
|
|
if (writeflag == MEM_READ) { |
472 |
|
|
odata = d->reg_0xc[node_nr]; |
473 |
|
|
debug("[ decxmi: (node %i) read from REG 0xC: " |
474 |
|
|
"0x%08x ]\n", node_nr, (int)odata); |
475 |
|
|
} else { |
476 |
|
|
d->reg_0xc[node_nr] = idata; |
477 |
|
|
debug("[ decxmi: (node %i) write to REG 0xC: " |
478 |
|
|
"0x%08x ]\n", node_nr, (int)idata); |
479 |
|
|
} |
480 |
|
|
break; |
481 |
|
|
default: |
482 |
|
|
if (writeflag==MEM_READ) { |
483 |
|
|
debug("[ decxmi: (node %i) read from unimplemented " |
484 |
|
|
"0x%08lx ]\n", node_nr, (long)relative_addr, |
485 |
|
|
(int)odata); |
486 |
|
|
} else { |
487 |
|
|
debug("[ decxmi: (node %i) write to unimplemented " |
488 |
|
|
"0x%08lx: 0x%08x ]\n", node_nr, |
489 |
|
|
(long)relative_addr, (int)idata); |
490 |
|
|
} |
491 |
|
|
} |
492 |
|
|
|
493 |
|
|
if (writeflag == MEM_READ) |
494 |
|
|
memory_writemax64(cpu, data, len, odata); |
495 |
|
|
|
496 |
|
|
return 1; |
497 |
|
|
} |
498 |
|
|
|
499 |
|
|
|
500 |
|
|
/* |
501 |
|
|
* dev_decxmi_init(): |
502 |
|
|
*/ |
503 |
|
|
void dev_decxmi_init(struct memory *mem, uint64_t baseaddr) |
504 |
|
|
{ |
505 |
|
|
struct decxmi_data *d; |
506 |
|
|
|
507 |
dpavlin |
42 |
CHECK_ALLOCATION(d = malloc(sizeof(struct decxmi_data))); |
508 |
dpavlin |
4 |
memset(d, 0, sizeof(struct decxmi_data)); |
509 |
|
|
|
510 |
|
|
memory_device_register(mem, "decxmi", baseaddr, DEV_DECXMI_LENGTH, |
511 |
dpavlin |
20 |
dev_decxmi_access, d, DM_DEFAULT, NULL); |
512 |
dpavlin |
4 |
} |
513 |
|
|
|