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/* |
/* |
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* Copyright (C) 2005 Anders Gavare. All rights reserved. |
* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: dev_cpc700.c,v 1.3 2005/11/22 02:07:39 debug Exp $ |
* $Id: dev_cpc700.c,v 1.7 2006/01/01 13:17:16 debug Exp $ |
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* |
* |
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* IBM CPC700 bridge; PCI and interrupt controller. |
* IBM CPC700 bridge; PCI and interrupt controller. |
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*/ |
*/ |
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/* |
/* |
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* dev_cpc700_pci_access(): |
* dev_cpc700_pci_access(): |
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* |
* |
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* Passes PCI indirect addr and data accesses onto bus_pci_access(). |
* Passes PCI indirect addr and data accesses onto bus_pci. |
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*/ |
*/ |
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int dev_cpc700_pci_access(struct cpu *cpu, struct memory *mem, |
DEVICE_ACCESS(cpc700_pci) |
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uint64_t relative_addr, unsigned char *data, size_t len, |
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int writeflag, void *extra) |
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{ |
{ |
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uint64_t idata = 0, odata = 0; |
uint64_t idata = 0, odata = 0; |
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int bus, dev, func, reg; |
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struct cpc700_data *d = extra; |
struct cpc700_data *d = extra; |
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if (writeflag == MEM_WRITE) |
if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len); |
idata = memory_readmax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN); |
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relative_addr += BUS_PCI_ADDR; |
switch (relative_addr) { |
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case 0: /* Address: */ |
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bus_pci_decompose_1(idata, &bus, &dev, &func, ®); |
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bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg); |
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break; |
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if (writeflag == MEM_WRITE) |
case 4: /* Data: */ |
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bus_pci_access(cpu, mem, relative_addr, &idata, |
bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ? |
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len, writeflag, d->pci_data); |
&odata : &idata, len, writeflag); |
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else |
break; |
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bus_pci_access(cpu, mem, relative_addr, &odata, |
} |
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len, writeflag, d->pci_data); |
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if (writeflag == MEM_READ) |
if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len, odata); |
memory_writemax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN, odata); |
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return 1; |
return 1; |
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} |
} |
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* |
* |
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* The interrupt controller. |
* The interrupt controller. |
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*/ |
*/ |
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int dev_cpc700_int_access(struct cpu *cpu, struct memory *mem, |
DEVICE_ACCESS(cpc700_int) |
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uint64_t relative_addr, unsigned char *data, size_t len, |
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int writeflag, void *extra) |
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{ |
{ |
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struct cpc700_data *d = extra; |
struct cpc700_data *d = extra; |
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uint64_t idata = 0, odata = 0; |
uint64_t idata = 0, odata = 0; |
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/* Register a PCI bus: */ |
/* Register a PCI bus: */ |
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d->pci_data = bus_pci_init( |
d->pci_data = bus_pci_init( |
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machine, |
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0 /* pciirq: TODO */, |
0 /* pciirq: TODO */, |
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0, /* pci device io offset */ |
0, /* pci device io offset */ |
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0, /* pci device mem offset */ |
0, /* pci device mem offset */ |