/[gxemul]/trunk/src/devices/dev_8253.c
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Contents of /trunk/src/devices/dev_8253.c

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Revision 42 - (show annotations)
Mon Oct 8 16:22:32 2007 UTC (16 years, 5 months ago) by dpavlin
File MIME type: text/plain
File size: 6960 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1613 2007/06/15 20:11:26 debug Exp $
20070501	Continuing a little on m88k disassembly (control registers,
		more instructions).
		Adding a dummy mvme88k machine mode.
20070502	Re-adding MIPS load/store alignment exceptions.
20070503	Implementing more of the M88K disassembly code.
20070504	Adding disassembly of some more M88K load/store instructions.
		Implementing some relatively simple M88K instructions (br.n,
		xor[.u] imm, and[.u] imm).
20070505	Implementing M88K three-register and, or, xor, and jmp[.n],
		bsr[.n] including function call trace stuff.
		Applying a patch from Bruce M. Simpson which implements the
		SYSCON_BOARD_CPU_CLOCK_FREQ_ID object of the syscon call in
		the yamon PROM emulation.
20070506	Implementing M88K bb0[.n] and bb1[.n], and skeletons for
		ldcr and stcr (although no control regs are implemented yet).
20070509	Found and fixed the bug which caused Linux for QEMU_MIPS to
		stop working in 0.4.5.1: It was a faulty change to the MIPS
		'sc' and 'scd' instructions I made while going through gcc -W
		warnings on 20070428.
20070510	Updating the Linux/QEMU_MIPS section in guestoses.html to
		use mips-test-0.2.tar.gz instead of 0.1.
		A big thank you to Miod Vallat for sending me M88K manuals.
		Implementing more M88K instructions (addu, subu, div[u], mulu,
		ext[u], clr, set, cmp).
20070511	Fixing bugs in the M88K "and" and "and.u" instructions (found
		by comparing against the manual).
		Implementing more M88K instructions (mask[.u], mak, bcnd (auto-
		generated)) and some more control register details.
		Cleanup: Removing the experimental AVR emulation mode and
		corresponding devices; AVR emulation wasn't really meaningful.
		Implementing autogeneration of most M88K loads/stores. The
		rectangle drawing demo (with -O0) for M88K runs :-)
		Beginning on M88K exception handling.
		More M88K instructions: tb0, tb1, rte, sub, jsr[.n].
		Adding some skeleton MVME PROM ("BUG") emulation.
20070512	Fixing a bug in the M88K cmp instruction.
		Adding the M88K lda (scaled register) instruction.
		Fixing bugs in 64-bit (32-bit pairs) M88K loads/stores.
		Removing the unused tick_hz stuff from the machine struct.
		Implementing the M88K xmem instruction. OpenBSD/mvme88k gets
		far enough to display the Copyright banner :-)
		Implementing subu.co (guess), addu.co, addu.ci, ff0, and ff1.
		Adding a dev_mvme187, for MVME187-specific devices/registers.
		OpenBSD/mvme88k prints more boot messages. :)
20070515	Continuing on MVME187 emulation (adding more devices, beginning
		on the CMMUs, etc).
		Adding the M88K and.c, xor.c, and or.c instructions, and making
		sure that mul, div, etc cause exceptions if executed when SFD1
		is disabled.
20070517	Continuing on M88K and MVME187 emulation in general; moving
		the CMMU registers to the CPU struct, separating dev_pcc2 from
		dev_mvme187, and beginning on memory_m88k.c (BATC and PATC).
		Fixing a bug in 64-bit (32-bit pairs) M88K fast stores.
		Implementing the clock part of dev_mk48txx.
		Implementing the M88K fstcr and xcr instructions.
		Implementing m88k_cpu_tlbdump().
		Beginning on the implementation of a separate address space
		for M88K .usr loads/stores.
20070520	Removing the non-working (skeleton) Sandpoint, SonyNEWS, SHARK
		Dnard, and Zaurus machine modes.
		Experimenting with dyntrans to_be_translated read-ahead. It
		seems to give a very small performance increase for MIPS
		emulation, but a large performance degradation for SuperH. Hm.
20070522	Disabling correct SuperH ITLB emulation; it does not seem to be
		necessary in order to let SH4 guest OSes run, and it slows down
		userspace code.
		Implementing "samepage" branches for SuperH emulation, and some
		other minor speed hacks.
20070525	Continuing on M88K memory-related stuff: exceptions, memory
		transaction register contents, etc.
		Implementing the M88K subu.ci instruction.
		Removing the non-working (skeleton) Iyonix machine mode.
		OpenBSD/mvme88k reaches userland :-), starts executing
		/sbin/init's instructions, and issues a few syscalls, before
		crashing.
20070526	Fixing bugs in dev_mk48txx, so that OpenBSD/mvme88k detects
		the correct time-of-day.
		Implementing a generic IRQ controller for the test machines
		(dev_irqc), similar to a proposed patch from Petr Stepan.
		Experimenting some more with translation read-ahead.
		Adding an "expect" script for automated OpenBSD/landisk
		install regression/performance tests.
20070527	Adding a dummy mmEye (SH3) machine mode skeleton.
		FINALLY found the strange M88K bug I have been hunting: I had
		not emulated the SNIP value for exceptions occurring in
		branch delay slots correctly.
		Implementing correct exceptions for 64-bit M88K loads/stores.
		Address to symbol lookups are now disabled when M88K is
		running in usermode (because usermode addresses don't have
		anything to do with supervisor addresses).
20070531	Removing the mmEye machine mode skeleton.
20070604	Some minor code cleanup.
20070605	Moving src/useremul.c into a subdir (src/useremul/), and
		cleaning up some more legacy constructs.
		Adding -Wstrict-aliasing and -fstrict-aliasing detection to
		the configure script.
20070606	Adding a check for broken GCC on Solaris to the configure
		script. (GCC 3.4.3 on Solaris cannot handle static variables
		which are initialized to 0 or NULL. :-/)
		Removing the old (non-working) ARC emulation modes: NEC RD94,
		R94, R96, and R98, and the last traces of Olivetti M700 and
		Deskstation Tyne.
		Removing the non-working skeleton WDSC device (dev_wdsc).
20070607	Thinking about how to use the host's cc + ld at runtime to
		generate native code. (See experiments/native_cc_ld_test.i
		for an example.)
20070608	Adding a program counter sampling timer, which could be useful
		for native code generation experiments.
		The KN02_CSR_NRMMOD bit in the DECstation 5000/200 (KN02) CSR
		should always be set, to allow a 5000/200 PROM to boot.
20070609	Moving out breakpoint details from the machine struct into
		a helper struct, and removing the limit on max nr of
		breakpoints.
20070610	Moving out tick functions into a helper struct as well (which
		also gets rid of the max limit).
20070612	FINALLY figured out why Debian/DECstation stopped working when
		translation read-ahead was enabled: in src/memory_rw.c, the
		call to invalidate_code_translation was made also if the
		memory access was an instruction load (if the page was mapped
		as writable); it shouldn't be called in that case.
20070613	Implementing some more MIPS32/64 revision 2 instructions: di,
		ei, ext, dext, dextm, dextu, and ins.
20070614	Implementing an instruction combination for the NetBSD/arm
		idle loop (making the host not use any cpu if NetBSD/arm
		inside the emulator is not using any cpu).
		Increasing the nr of ARM VPH entries from 128 to 384.
20070615	Removing the ENABLE_arch stuff from the configure script, so
		that all included architectures are included in both release
		and development builds.
		Moving memory related helper functions from misc.c to memory.c.
		Adding preliminary instructions for netbooting NetBSD/pmppc to
		guestoses.html; it doesn't work yet, there are weird timeouts.
		Beginning a total rewrite of the userland emulation modes
		(removing all emulation modes, beginning from scratch with
		NetBSD/MIPS and FreeBSD/Alpha only).
20070616	After fixing a bug in the DEC21143 NIC (the TDSTAT_OWN bit was
		only cleared for the last segment when transmitting, not all
		segments), NetBSD/pmppc boots with root-on-nfs without the
		timeouts. Updating guestoses.html.
		Removing the skeleton PSP (Playstation Portable) mode.
		Moving X11-related stuff in the machine struct into a helper
		struct.
		Cleanup of out-of-memory checks, to use a new CHECK_ALLOCATION
		macro (which prints a meaningful error message).
		Adding a COMMENT to each machine and device (for automagic
		.index comment generation).
		Doing regression testing for the next release.

==============  RELEASE 0.4.6  ==============


1 /*
2 * Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: dev_8253.c,v 1.20 2007/06/15 18:13:04 debug Exp $
29 *
30 * COMMENT: Intel 8253/8254 Programmable Interval Timer
31 *
32 * TODO/NOTE:
33 * The timers don't really count down. Timer 0 causes clock interrupts
34 * at a specific frequency, but reading the counter register would not
35 * result in anything meaningful.
36 *
37 * (Split counter[] into reset value and current value.)
38 */
39
40 #include <stdio.h>
41 #include <stdlib.h>
42 #include <string.h>
43
44 #include "cpu.h"
45 #include "device.h"
46 #include "emul.h"
47 #include "interrupt.h"
48 #include "machine.h"
49 #include "memory.h"
50 #include "misc.h"
51 #include "timer.h"
52
53 #include "i8253reg.h"
54
55
56 /* #define debug fatal */
57
58 #define DEV_8253_LENGTH 4
59 #define TICK_SHIFT 14
60
61
62 struct pit8253_data {
63 int in_use;
64
65 int counter_select;
66 uint8_t mode_byte;
67
68 int mode[3];
69 int counter[3];
70
71 int hz[3];
72
73 struct timer *timer0;
74 struct interrupt irq;
75 int pending_interrupts_timer0;
76 };
77
78
79 static void timer0_tick(struct timer *t, void *extra)
80 {
81 struct pit8253_data *d = extra;
82 d->pending_interrupts_timer0 ++;
83
84 /* printf("%i ", d->pending_interrupts_timer0); fflush(stdout); */
85 }
86
87
88 DEVICE_TICK(8253)
89 {
90 struct pit8253_data *d = extra;
91
92 if (!d->in_use)
93 return;
94
95 switch (d->mode[0] & 0x0e) {
96
97 case I8253_TIMER_INTTC:
98 if (d->pending_interrupts_timer0 > 0)
99 INTERRUPT_ASSERT(d->irq);
100 break;
101
102 case I8253_TIMER_SQWAVE:
103 case I8253_TIMER_RATEGEN:
104 break;
105
106 default:fatal("[ 8253: unimplemented mode 0x%x ]\n", d->mode[0] & 0x0e);
107 exit(1);
108 }
109 }
110
111
112 DEVICE_ACCESS(8253)
113 {
114 struct pit8253_data *d = (struct pit8253_data *) extra;
115 uint64_t idata = 0, odata = 0;
116
117 if (writeflag == MEM_WRITE)
118 idata = memory_readmax64(cpu, data, len);
119
120 d->in_use = 1;
121
122 switch (relative_addr) {
123
124 case I8253_TIMER_CNTR0:
125 case I8253_TIMER_CNTR1:
126 case I8253_TIMER_CNTR2:
127 if (writeflag == MEM_WRITE) {
128 switch (d->mode_byte & 0x30) {
129 case I8253_TIMER_LSB:
130 case I8253_TIMER_16BIT:
131 d->counter[relative_addr] &= 0xff00;
132 d->counter[relative_addr] |= (idata & 0xff);
133 break;
134 case I8253_TIMER_MSB:
135 d->counter[relative_addr] &= 0x00ff;
136 d->counter[relative_addr] |= ((idata&0xff)<<8);
137 if (d->counter[relative_addr] != 0)
138 d->hz[relative_addr] =
139 I8253_TIMER_FREQ / (float)
140 d->counter[relative_addr] + 0.5;
141 else
142 d->hz[relative_addr] = 0;
143 debug("[ 8253: counter %i set to %i (%i Hz) "
144 "]\n", relative_addr, d->counter[
145 relative_addr], d->hz[relative_addr]);
146 switch (relative_addr) {
147 case 0: if (d->timer0 == NULL)
148 d->timer0 = timer_add(
149 d->hz[0], timer0_tick, d);
150 else
151 timer_update_frequency(
152 d->timer0, d->hz[0]);
153 break;
154 case 1: fatal("TODO: DMA refresh?\n");
155 exit(1);
156 case 2: fatal("TODO: 8253 tone generation?\n");
157 break;
158 }
159 break;
160 default:fatal("[ 8253: huh? writing to counter"
161 " %i but neither from msb nor lsb? ]\n",
162 relative_addr);
163 }
164 } else {
165 switch (d->mode_byte & 0x30) {
166 case I8253_TIMER_LSB:
167 case I8253_TIMER_16BIT:
168 odata = d->counter[relative_addr] & 0xff;
169 break;
170 case I8253_TIMER_MSB:
171 odata = (d->counter[relative_addr] >> 8) & 0xff;
172 break;
173 default:fatal("[ 8253: huh? reading from counter"
174 " %i but neither from msb nor lsb? ]\n",
175 relative_addr);
176 }
177 }
178
179 /* Switch from LSB to MSB, if accessing as 16-bit word: */
180 if ((d->mode_byte & 0x30) == I8253_TIMER_16BIT)
181 d->mode_byte &= ~I8253_TIMER_LSB;
182
183 break;
184
185 case I8253_TIMER_MODE:
186 if (writeflag == MEM_WRITE) {
187 d->mode_byte = idata;
188
189 d->counter_select = idata >> 6;
190 if (d->counter_select > 2) {
191 debug("[ 8253: attempt to select counter 3,"
192 " which doesn't exist. ]\n");
193 d->counter_select = 0;
194 }
195
196 d->mode[d->counter_select] = idata & 0x0e;
197
198 debug("[ 8253: select=%i mode=0x%x ",
199 d->counter_select, d->mode[d->counter_select]);
200 if (idata & 0x30) {
201 switch (idata & 0x30) {
202 case I8253_TIMER_LSB:
203 debug("LSB ");
204 break;
205 case I8253_TIMER_16BIT:
206 debug("LSB+");
207 case I8253_TIMER_MSB:
208 debug("MSB ");
209 }
210 }
211 debug("]\n");
212
213 if (idata & I8253_TIMER_BCD) {
214 fatal("[ 8253: BCD not yet implemented ]\n");
215 exit(1);
216 }
217 } else {
218 debug("[ 8253: read; can this actually happen? ]\n");
219 odata = d->mode_byte;
220 }
221 break;
222
223 default:if (writeflag == MEM_WRITE) {
224 fatal("[ 8253: unimplemented write to address 0x%x"
225 " data=0x%02x ]\n", (int)relative_addr, (int)idata);
226 } else {
227 fatal("[ 8253: unimplemented read from address 0x%x "
228 "]\n", (int)relative_addr);
229 }
230 exit(1);
231 }
232
233 if (writeflag == MEM_READ)
234 memory_writemax64(cpu, data, len, odata);
235
236 return 1;
237 }
238
239
240 DEVINIT(8253)
241 {
242 struct pit8253_data *d;
243
244 CHECK_ALLOCATION(d = malloc(sizeof(struct pit8253_data)));
245 memset(d, 0, sizeof(struct pit8253_data));
246
247 d->in_use = devinit->in_use;
248
249 INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
250
251 /* Don't cause interrupt, by default. */
252 d->mode[0] = I8253_TIMER_RATEGEN;
253 d->mode[1] = I8253_TIMER_RATEGEN;
254 d->mode[2] = I8253_TIMER_RATEGEN;
255
256 devinit->machine->isa_pic_data.pending_timer_interrupts =
257 &d->pending_interrupts_timer0;
258
259 memory_device_register(devinit->machine->memory, devinit->name,
260 devinit->addr, DEV_8253_LENGTH, dev_8253_access, (void *)d,
261 DM_DEFAULT, NULL);
262
263 machine_add_tickfunction(devinit->machine, dev_8253_tick,
264 d, TICK_SHIFT);
265
266 return 1;
267 }
268

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