src/devices/dev_8253.c

/*
 *  Copyright (C) 2005-2007  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *   
 *
 *  $Id: dev_8253.c,v 1.18 2006/12/30 13:30:57 debug Exp $
 *
 *  Intel 8253/8254 Programmable Interval Timer
 *
 *  TODO/NOTE:
 *      The timers don't really count down. Timer 0 causes clock interrupts
 *      at a specific frequency, but reading the counter register would not
 *      result in anything meaningful.
 *
 *  (Split counter[] into reset value and current value.)
 */

#include <stdio.h>
#include <stdlib.h>
#include <string.h>

#include "cpu.h"
#include "device.h"
#include "emul.h"
#include "interrupt.h"
#include "machine.h"
#include "memory.h"
#include "misc.h"
#include "timer.h"

#include "i8253reg.h"


#define debug fatal

#define DEV_8253_LENGTH         4
#define TICK_SHIFT              14


struct pit8253_data {
        int             in_use;

        int             counter_select;
        uint8_t         mode_byte;

        int             mode[3];
        int             counter[3];

        int             hz[3];

        struct timer    *timer0;
        struct interrupt irq;
        int             pending_interrupts_timer0;
};


static void timer0_tick(struct timer *t, void *extra)
{
        struct pit8253_data *d = (struct pit8253_data *) extra;
        d->pending_interrupts_timer0 ++;

#if 0
        printf("%i ", d->pending_interrupts_timer0); fflush(stdout);
#endif
}


DEVICE_TICK(8253)
{
        struct pit8253_data *d = (struct pit8253_data *) extra;

        if (!d->in_use)
                return;

        switch (d->mode[0] & 0x0e) {

        case I8253_TIMER_INTTC:
                if (d->pending_interrupts_timer0 > 0)
                        INTERRUPT_ASSERT(d->irq);
                break;

        case I8253_TIMER_SQWAVE:
        case I8253_TIMER_RATEGEN:
                break;

        default:fatal("[ 8253: unimplemented mode 0x%x ]\n", d->mode[0] & 0x0e);
                exit(1);
        }
}


DEVICE_ACCESS(8253)
{
        struct pit8253_data *d = (struct pit8253_data *) extra;
        uint64_t idata = 0, odata = 0;

        if (writeflag == MEM_WRITE)
                idata = memory_readmax64(cpu, data, len);

        d->in_use = 1;

        switch (relative_addr) {

        case I8253_TIMER_CNTR0:
        case I8253_TIMER_CNTR1:
        case I8253_TIMER_CNTR2:
                if (writeflag == MEM_WRITE) {
                        switch (d->mode_byte & 0x30) {
                        case I8253_TIMER_LSB:
                        case I8253_TIMER_16BIT:
                                d->counter[relative_addr] &= 0xff00;
                                d->counter[relative_addr] |= (idata & 0xff);
                                break;
                        case I8253_TIMER_MSB:
                                d->counter[relative_addr] &= 0x00ff;
                                d->counter[relative_addr] |= ((idata&0xff)<<8);
                                if (d->counter[relative_addr] != 0)
                                        d->hz[relative_addr] =
                                            I8253_TIMER_FREQ / (float)
                                            d->counter[relative_addr] + 0.5;
                                else
                                        d->hz[relative_addr] = 0;
                                debug("[ 8253: counter %i set to %i (%i Hz) "
                                    "]\n", relative_addr, d->counter[
                                    relative_addr], d->hz[relative_addr]);
                                switch (relative_addr) {
                                case 0: if (d->timer0 == NULL)
                                                d->timer0 = timer_add(
                                                    d->hz[0], timer0_tick, d);
                                        else
                                                timer_update_frequency(
                                                    d->timer0, d->hz[0]);
                                        break;
                                case 1: fatal("TODO: DMA refresh?\n");
                                        exit(1);
                                case 2: fatal("TODO: 8253 tone generation?\n");
                                        break;
                                }
                                break;
                        default:fatal("[ 8253: huh? writing to counter"
                                    " %i but neither from msb nor lsb? ]\n",
                                    relative_addr);
                        }
                } else {
                        switch (d->mode_byte & 0x30) {
                        case I8253_TIMER_LSB:
                        case I8253_TIMER_16BIT:
                                odata = d->counter[relative_addr] & 0xff;
                                break;
                        case I8253_TIMER_MSB:
                                odata = (d->counter[relative_addr] >> 8) & 0xff;
                                break;
                        default:fatal("[ 8253: huh? reading from counter"
                                    " %i but neither from msb nor lsb? ]\n",
                                    relative_addr);
                        }
                }

                /*  Switch from LSB to MSB, if accessing as 16-bit word:  */
                if ((d->mode_byte & 0x30) == I8253_TIMER_16BIT)
                        d->mode_byte &= ~I8253_TIMER_LSB;

                break;

        case I8253_TIMER_MODE:
                if (writeflag == MEM_WRITE) {
                        d->mode_byte = idata;

                        d->counter_select = idata >> 6;
                        if (d->counter_select > 2) {
                                debug("[ 8253: attempt to select counter 3,"
                                    " which doesn't exist. ]\n");
                                d->counter_select = 0;
                        }

                        d->mode[d->counter_select] = idata & 0x0e;

                        debug("[ 8253: select=%i mode=0x%x ",
                            d->counter_select, d->mode[d->counter_select]);
                        if (idata & 0x30) {
                                switch (idata & 0x30) {
                                case I8253_TIMER_LSB:
                                        debug("LSB ");
                                        break;
                                case I8253_TIMER_16BIT:
                                        debug("LSB+");
                                case I8253_TIMER_MSB:
                                        debug("MSB ");
                                }
                        }
                        debug("]\n");

                        if (idata & I8253_TIMER_BCD) {
                                fatal("[ 8253: BCD not yet implemented ]\n");
                                exit(1);
                        }
                } else {
                        debug("[ 8253: read; can this actually happen? ]\n");
                        odata = d->mode_byte;
                }
                break;

        default:if (writeflag == MEM_WRITE) {
                        fatal("[ 8253: unimplemented write to address 0x%x"
                            " data=0x%02x ]\n", (int)relative_addr, (int)idata);
                } else {
                        fatal("[ 8253: unimplemented read from address 0x%x "
                            "]\n", (int)relative_addr);
                }
                exit(1);
        }

        if (writeflag == MEM_READ)
                memory_writemax64(cpu, data, len, odata);

        return 1;
}


DEVINIT(8253)
{
        struct pit8253_data *d = malloc(sizeof(struct pit8253_data));

        if (d == NULL) {
                fprintf(stderr, "out of memory\n");
                exit(1);
        }
        memset(d, 0, sizeof(struct pit8253_data));

        d->in_use = devinit->in_use;

        INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);

        /*  Don't cause interrupt, by default.  */
        d->mode[0] = I8253_TIMER_RATEGEN;
        d->mode[1] = I8253_TIMER_RATEGEN;
        d->mode[2] = I8253_TIMER_RATEGEN;

        devinit->machine->isa_pic_data.pending_timer_interrupts =
            &d->pending_interrupts_timer0;

        memory_device_register(devinit->machine->memory, devinit->name,
            devinit->addr, DEV_8253_LENGTH, dev_8253_access, (void *)d,
            DM_DEFAULT, NULL);

        machine_add_tickfunction(devinit->machine, dev_8253_tick,
            d, TICK_SHIFT, 0.0);

        return 1;
}

1	/*
2	* Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
3	*
4	* Redistribution and use in source and binary forms, with or without
5	* modification, are permitted provided that the following conditions are met:
6	*
7	* 1. Redistributions of source code must retain the above copyright
8	* notice, this list of conditions and the following disclaimer.
9	* 2. Redistributions in binary form must reproduce the above copyright
10	* notice, this list of conditions and the following disclaimer in the
11	* documentation and/or other materials provided with the distribution.
12	* 3. The name of the author may not be used to endorse or promote products
13	* derived from this software without specific prior written permission.
14	*
15	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25	* SUCH DAMAGE.
26	*
27	*
28	* $Id: dev_8253.c,v 1.18 2006/12/30 13:30:57 debug Exp $
29	*
30	* Intel 8253/8254 Programmable Interval Timer
31	*
32	* TODO/NOTE:
33	* The timers don't really count down. Timer 0 causes clock interrupts
34	* at a specific frequency, but reading the counter register would not
35	* result in anything meaningful.
36	*
37	* (Split counter[] into reset value and current value.)
38	*/
39
40	#include <stdio.h>
41	#include <stdlib.h>
42	#include <string.h>
43
44	#include "cpu.h"
45	#include "device.h"
46	#include "emul.h"
47	#include "interrupt.h"
48	#include "machine.h"
49	#include "memory.h"
50	#include "misc.h"
51	#include "timer.h"
52
53	#include "i8253reg.h"
54
55
56	#define debug fatal
57
58	#define DEV_8253_LENGTH 4
59	#define TICK_SHIFT 14
60
61
62	struct pit8253_data {
63	int in_use;
64
65	int counter_select;
66	uint8_t mode_byte;
67
68	int mode[3];
69	int counter[3];
70
71	int hz[3];
72
73	struct timer *timer0;
74	struct interrupt irq;
75	int pending_interrupts_timer0;
76	};
77
78
79	static void timer0_tick(struct timer t, void extra)
80	{
81	struct pit8253_data d = (struct pit8253_data ) extra;
82	d->pending_interrupts_timer0 ++;
83
84	#if 0
85	printf("%i ", d->pending_interrupts_timer0); fflush(stdout);
86	#endif
87	}
88
89
90	DEVICE_TICK(8253)
91	{
92	struct pit8253_data d = (struct pit8253_data ) extra;
93
94	if (!d->in_use)
95	return;
96
97	switch (d->mode[0] & 0x0e) {
98
99	case I8253_TIMER_INTTC:
100	if (d->pending_interrupts_timer0 > 0)
101	INTERRUPT_ASSERT(d->irq);
102	break;
103
104	case I8253_TIMER_SQWAVE:
105	case I8253_TIMER_RATEGEN:
106	break;
107
108	default:fatal("[ 8253: unimplemented mode 0x%x ]\n", d->mode[0] & 0x0e);
109	exit(1);
110	}
111	}
112
113
114	DEVICE_ACCESS(8253)
115	{
116	struct pit8253_data d = (struct pit8253_data ) extra;
117	uint64_t idata = 0, odata = 0;
118
119	if (writeflag == MEM_WRITE)
120	idata = memory_readmax64(cpu, data, len);
121
122	d->in_use = 1;
123
124	switch (relative_addr) {
125
126	case I8253_TIMER_CNTR0:
127	case I8253_TIMER_CNTR1:
128	case I8253_TIMER_CNTR2:
129	if (writeflag == MEM_WRITE) {
130	switch (d->mode_byte & 0x30) {
131	case I8253_TIMER_LSB:
132	case I8253_TIMER_16BIT:
133	d->counter[relative_addr] &= 0xff00;
134	d->counter[relative_addr] \|= (idata & 0xff);
135	break;
136	case I8253_TIMER_MSB:
137	d->counter[relative_addr] &= 0x00ff;
138	d->counter[relative_addr] \|= ((idata&0xff)<<8);
139	if (d->counter[relative_addr] != 0)
140	d->hz[relative_addr] =
141	I8253_TIMER_FREQ / (float)
142	d->counter[relative_addr] + 0.5;
143	else
144	d->hz[relative_addr] = 0;
145	debug("[ 8253: counter %i set to %i (%i Hz) "
146	"]\n", relative_addr, d->counter[
147	relative_addr], d->hz[relative_addr]);
148	switch (relative_addr) {
149	case 0: if (d->timer0 == NULL)
150	d->timer0 = timer_add(
151	d->hz[0], timer0_tick, d);
152	else
153	timer_update_frequency(
154	d->timer0, d->hz[0]);
155	break;
156	case 1: fatal("TODO: DMA refresh?\n");
157	exit(1);
158	case 2: fatal("TODO: 8253 tone generation?\n");
159	break;
160	}
161	break;
162	default:fatal("[ 8253: huh? writing to counter"
163	" %i but neither from msb nor lsb? ]\n",
164	relative_addr);
165	}
166	} else {
167	switch (d->mode_byte & 0x30) {
168	case I8253_TIMER_LSB:
169	case I8253_TIMER_16BIT:
170	odata = d->counter[relative_addr] & 0xff;
171	break;
172	case I8253_TIMER_MSB:
173	odata = (d->counter[relative_addr] >> 8) & 0xff;
174	break;
175	default:fatal("[ 8253: huh? reading from counter"
176	" %i but neither from msb nor lsb? ]\n",
177	relative_addr);
178	}
179	}
180
181	/* Switch from LSB to MSB, if accessing as 16-bit word: */
182	if ((d->mode_byte & 0x30) == I8253_TIMER_16BIT)
183	d->mode_byte &= ~I8253_TIMER_LSB;
184
185	break;
186
187	case I8253_TIMER_MODE:
188	if (writeflag == MEM_WRITE) {
189	d->mode_byte = idata;
190
191	d->counter_select = idata >> 6;
192	if (d->counter_select > 2) {
193	debug("[ 8253: attempt to select counter 3,"
194	" which doesn't exist. ]\n");
195	d->counter_select = 0;
196	}
197
198	d->mode[d->counter_select] = idata & 0x0e;
199
200	debug("[ 8253: select=%i mode=0x%x ",
201	d->counter_select, d->mode[d->counter_select]);
202	if (idata & 0x30) {
203	switch (idata & 0x30) {
204	case I8253_TIMER_LSB:
205	debug("LSB ");
206	break;
207	case I8253_TIMER_16BIT:
208	debug("LSB+");
209	case I8253_TIMER_MSB:
210	debug("MSB ");
211	}
212	}
213	debug("]\n");
214
215	if (idata & I8253_TIMER_BCD) {
216	fatal("[ 8253: BCD not yet implemented ]\n");
217	exit(1);
218	}
219	} else {
220	debug("[ 8253: read; can this actually happen? ]\n");
221	odata = d->mode_byte;
222	}
223	break;
224
225	default:if (writeflag == MEM_WRITE) {
226	fatal("[ 8253: unimplemented write to address 0x%x"
227	" data=0x%02x ]\n", (int)relative_addr, (int)idata);
228	} else {
229	fatal("[ 8253: unimplemented read from address 0x%x "
230	"]\n", (int)relative_addr);
231	}
232	exit(1);
233	}
234
235	if (writeflag == MEM_READ)
236	memory_writemax64(cpu, data, len, odata);
237
238	return 1;
239	}
240
241
242	DEVINIT(8253)
243	{
244	struct pit8253_data *d = malloc(sizeof(struct pit8253_data));
245
246	if (d == NULL) {
247	fprintf(stderr, "out of memory\n");
248	exit(1);
249	}
250	memset(d, 0, sizeof(struct pit8253_data));
251
252	d->in_use = devinit->in_use;
253
254	INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
255
256	/* Don't cause interrupt, by default. */
257	d->mode[0] = I8253_TIMER_RATEGEN;
258	d->mode[1] = I8253_TIMER_RATEGEN;
259	d->mode[2] = I8253_TIMER_RATEGEN;
260
261	devinit->machine->isa_pic_data.pending_timer_interrupts =
262	&d->pending_interrupts_timer0;
263
264	memory_device_register(devinit->machine->memory, devinit->name,
265	devinit->addr, DEV_8253_LENGTH, dev_8253_access, (void *)d,
266	DM_DEFAULT, NULL);
267
268	machine_add_tickfunction(devinit->machine, dev_8253_tick,
269	d, TICK_SHIFT, 0.0);
270
271	return 1;
272	}
273