25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: memory_arm.c,v 1.23 2005/10/07 15:19:48 debug Exp $ |
* $Id: memory_arm.c,v 1.27 2005/10/23 14:24:13 debug Exp $ |
29 |
* |
* |
30 |
* |
* |
31 |
* TODO/NOTE: There are probably two solutions to the subpage access |
* TODO/NOTE: The B and/or C bits could also cause the return value to |
32 |
* permission problem: |
* be MEMORY_NOT_FULL_PAGE, to make sure it doesn't get entered into the |
33 |
* |
* translation arrays. TODO: Find out if this is a good thing to do. |
|
* a) the obvious (almost trivial) solution is to decrease the native page |
|
|
* size from 4 KB to 1 KB. That would ruin the rest of the translation |
|
|
* system though. (It would be infeasible to hold the entire address |
|
|
* space in 1-level tables.) |
|
|
* |
|
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* b) to return something else than just 0, 1, or 2 from arm_memory_rw(). |
|
|
* Perhaps |4, which would indicate that the vaddr => paddr conversion |
|
|
* was done, but that it should not be entered into the cache. This could |
|
|
* also be used in combination with the B and C bits (which are currently |
|
|
* ignored). |
|
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* |
|
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* b would probably be the best solution. |
|
34 |
*/ |
*/ |
35 |
|
|
36 |
#include <stdio.h> |
#include <stdio.h> |
47 |
|
|
48 |
|
|
49 |
/* |
/* |
50 |
|
* arm_translate_address(): |
51 |
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* |
52 |
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* Address translation with the MMU disabled. |
53 |
|
*/ |
54 |
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int arm_translate_address(struct cpu *cpu, uint64_t vaddr64, |
55 |
|
uint64_t *return_addr, int flags) |
56 |
|
{ |
57 |
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*return_addr = vaddr64 & 0xffffffff; |
58 |
|
return 2; |
59 |
|
} |
60 |
|
|
61 |
|
|
62 |
|
/* |
63 |
* arm_check_access(): |
* arm_check_access(): |
64 |
* |
* |
65 |
* Helper function. Returns 0 for no access, 1 for read-only, and 2 for |
* Helper function. Returns 0 for no access, 1 for read-only, and 2 for |
100 |
|
|
101 |
|
|
102 |
/* |
/* |
103 |
* arm_translate_address(): |
* arm_translate_address_mmu(): |
104 |
* |
* |
105 |
* Don't call this function is userland_emul is non-NULL, or cpu is NULL. |
* Don't call this function is userland_emul is non-NULL, or cpu is NULL. |
106 |
* |
* |
108 |
* 0 Failure |
* 0 Failure |
109 |
* 1 Success, the page is readable only |
* 1 Success, the page is readable only |
110 |
* 2 Success, the page is read/write |
* 2 Success, the page is read/write |
111 |
|
* |
112 |
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* If this is a 1KB page access, then the return value is ORed with |
113 |
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* MEMORY_NOT_FULL_PAGE. |
114 |
*/ |
*/ |
115 |
int arm_translate_address(struct cpu *cpu, uint64_t vaddr64, |
int arm_translate_address_mmu(struct cpu *cpu, uint64_t vaddr64, |
116 |
uint64_t *return_addr, int flags) |
uint64_t *return_addr, int flags) |
117 |
{ |
{ |
118 |
unsigned char descr[4]; |
unsigned char *q; |
119 |
uint32_t addr, d, d2 = (uint32_t)(int32_t)-1, ptba, vaddr = vaddr64; |
uint32_t addr, d=0, d2 = (uint32_t)(int32_t)-1, ptba, vaddr = vaddr64; |
|
int d2_in_use = 0, d_in_use = 1; |
|
120 |
int instr = flags & FLAG_INSTR; |
int instr = flags & FLAG_INSTR; |
121 |
int writeflag = (flags & FLAG_WRITEFLAG)? 1 : 0; |
int writeflag = (flags & FLAG_WRITEFLAG)? 1 : 0; |
122 |
int useraccess = flags & MEMORY_USER_ACCESS; |
int useraccess = flags & MEMORY_USER_ACCESS; |
124 |
int user = (cpu->cd.arm.cpsr & ARM_FLAG_MODE) == ARM_MODE_USR32; |
int user = (cpu->cd.arm.cpsr & ARM_FLAG_MODE) == ARM_MODE_USR32; |
125 |
int domain, dav, ap0,ap1,ap2,ap3, ap = 0, access = 0; |
int domain, dav, ap0,ap1,ap2,ap3, ap = 0, access = 0; |
126 |
int fs = 2; /* fault status (2 = terminal exception) */ |
int fs = 2; /* fault status (2 = terminal exception) */ |
127 |
|
int subpage = 0; |
|
if (!(cpu->cd.arm.control & ARM_CONTROL_MMU)) { |
|
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*return_addr = vaddr; |
|
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return 2; |
|
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} |
|
128 |
|
|
129 |
if (useraccess) |
if (useraccess) |
130 |
user = 1; |
user = 1; |
131 |
|
|
132 |
addr = cpu->cd.arm.ttb + ((vaddr & 0xfff00000ULL) >> 18); |
addr = ((vaddr & 0xfff00000ULL) >> 18); |
133 |
if (!cpu->memory_rw(cpu, cpu->mem, addr, &descr[0], |
|
134 |
sizeof(descr), MEM_READ, PHYSICAL | NO_EXCEPTIONS)) { |
if (cpu->cd.arm.translation_table == NULL || |
135 |
fatal("arm_translate_address(): huh?\n"); |
cpu->cd.arm.ttb != cpu->cd.arm.last_ttb) { |
136 |
exit(1); |
uint32_t ofs; |
137 |
|
cpu->cd.arm.translation_table = memory_paddr_to_hostaddr( |
138 |
|
cpu->mem, cpu->cd.arm.ttb & 0x0fffffff, 0); |
139 |
|
if (cpu->cd.arm.translation_table != NULL) { |
140 |
|
ofs = cpu->cd.arm.ttb & ((1 << BITS_PER_MEMBLOCK) - 1); |
141 |
|
cpu->cd.arm.translation_table += ofs; |
142 |
|
} |
143 |
|
cpu->cd.arm.last_ttb = cpu->cd.arm.ttb; |
144 |
} |
} |
|
if (cpu->byte_order == EMUL_LITTLE_ENDIAN) |
|
|
d = descr[0] + (descr[1] << 8) + (descr[2] << 16) |
|
|
+ (descr[3] << 24); |
|
|
else |
|
|
d = descr[3] + (descr[2] << 8) + (descr[1] << 16) |
|
|
+ (descr[0] << 24); |
|
145 |
|
|
146 |
/* fatal("vaddr=0x%08x ttb=0x%08x addr=0x%08x d=0x%08x\n", |
if (cpu->cd.arm.translation_table != NULL) { |
147 |
vaddr, cpu->cd.arm.ttb, addr, d); */ |
d = *(uint32_t *)(cpu->cd.arm.translation_table + addr); |
148 |
|
#ifdef HOST_LITTLE_ENDIAN |
149 |
|
if (cpu->byte_order == EMUL_BIG_ENDIAN) |
150 |
|
#else |
151 |
|
if (cpu->byte_order == EMUL_LITTLE_ENDIAN) |
152 |
|
#endif |
153 |
|
d = ((d & 0xff) << 24) | ((d & 0xff00) << 8) | |
154 |
|
((d & 0xff0000) >> 8) | ((d & 0xff000000) >> 24); |
155 |
|
} |
156 |
|
|
157 |
/* Get the domain from the descriptor, and the Domain Access Value: */ |
/* Get the domain from the descriptor, and the Domain Access Value: */ |
158 |
domain = (d >> 5) & 15; |
domain = (d >> 5) & 15; |
160 |
|
|
161 |
switch (d & 3) { |
switch (d & 3) { |
162 |
|
|
163 |
case 0: d_in_use = 0; |
case 0: domain = 0; |
|
domain = 0; |
|
164 |
fs = FAULT_TRANS_S; |
fs = FAULT_TRANS_S; |
165 |
goto exception_return; |
goto exception_return; |
166 |
|
|
167 |
case 1: /* Course Pagetable: */ |
case 1: /* Course Pagetable: */ |
168 |
|
if (dav == 0) { |
169 |
|
fs = FAULT_DOMAIN_P; |
170 |
|
goto exception_return; |
171 |
|
} |
172 |
ptba = d & 0xfffffc00; |
ptba = d & 0xfffffc00; |
173 |
addr = ptba + ((vaddr & 0x000ff000) >> 10); |
addr = ptba + ((vaddr & 0x000ff000) >> 10); |
174 |
if (!cpu->memory_rw(cpu, cpu->mem, addr, &descr[0], |
|
175 |
sizeof(descr), MEM_READ, PHYSICAL | NO_EXCEPTIONS)) { |
q = memory_paddr_to_hostaddr(cpu->mem, addr & 0x0fffffff, 0); |
176 |
fatal("arm_translate_address(): huh 2?\n"); |
if (q == NULL) { |
177 |
|
printf("arm memory blah blah adfh asfg asdgasdg\n"); |
178 |
exit(1); |
exit(1); |
179 |
} |
} |
180 |
|
d2 = *(uint32_t *)(q + (addr & ((1 << BITS_PER_MEMBLOCK) - 1))); |
181 |
|
#ifdef HOST_LITTLE_ENDIAN |
182 |
|
if (cpu->byte_order == EMUL_BIG_ENDIAN) |
183 |
|
#else |
184 |
if (cpu->byte_order == EMUL_LITTLE_ENDIAN) |
if (cpu->byte_order == EMUL_LITTLE_ENDIAN) |
185 |
d2 = descr[0] + (descr[1] << 8) + (descr[2] << 16) |
#endif |
186 |
+ (descr[3] << 24); |
d2 = ((d2 & 0xff) << 24) | ((d2 & 0xff00) << 8) | |
187 |
else |
((d2 & 0xff0000) >> 8) | ((d2 & 0xff000000) >> 24); |
|
d2 = descr[3] + (descr[2] << 8) + (descr[1] << 16) |
|
|
+ (descr[0] << 24); |
|
|
d2_in_use = 1; |
|
188 |
|
|
189 |
switch (d2 & 3) { |
switch (d2 & 3) { |
190 |
case 0: fs = FAULT_TRANS_P; |
case 0: fs = FAULT_TRANS_P; |
210 |
case 0x800: ap = ap2; break; |
case 0x800: ap = ap2; break; |
211 |
default: ap = ap3; |
default: ap = ap3; |
212 |
} |
} |
213 |
#if 0 |
if (ap0 != ap1 || ap0 != ap2 || ap0 != ap3) |
214 |
if ((ap0 != ap1 || ap0 != ap2 || ap0 != ap3) && |
subpage = 1; |
|
!no_exceptions) |
|
|
fatal("WARNING: vaddr = 0x%08x, small page, but" |
|
|
" different access permissions for the sub" |
|
|
"pages! This is not really implemented " |
|
|
"yet.\n", (int)vaddr); |
|
|
#endif |
|
215 |
*return_addr = (d2 & 0xfffff000) | (vaddr & 0x00000fff); |
*return_addr = (d2 & 0xfffff000) | (vaddr & 0x00000fff); |
216 |
break; |
break; |
217 |
case 3: /* 1KB page: */ |
case 3: /* 1KB page: */ |
218 |
fatal("WARNING: 1 KB page! Not implemented yet.\n"); |
subpage = 1; |
219 |
ap = (d2 >> 4) & 3; |
ap = (d2 >> 4) & 3; |
220 |
*return_addr = (d2 & 0xfffffc00) | (vaddr & 0x000003ff); |
*return_addr = (d2 & 0xfffffc00) | (vaddr & 0x000003ff); |
221 |
break; |
break; |
222 |
} |
} |
|
if (dav == 0) { |
|
|
fs = FAULT_DOMAIN_P; |
|
|
goto exception_return; |
|
|
} |
|
223 |
access = arm_check_access(cpu, ap, dav, user); |
access = arm_check_access(cpu, ap, dav, user); |
224 |
if (access > writeflag) |
if (access > writeflag) |
225 |
return access; |
return access | (subpage? MEMORY_NOT_FULL_PAGE : 0); |
226 |
fs = FAULT_PERM_P; |
fs = FAULT_PERM_P; |
227 |
goto exception_return; |
goto exception_return; |
228 |
|
|
229 |
case 2: /* Section descriptor: */ |
case 2: /* Section descriptor: */ |
|
*return_addr = (d & 0xfff00000) | (vaddr & 0x000fffff); |
|
230 |
if (dav == 0) { |
if (dav == 0) { |
231 |
fs = FAULT_DOMAIN_S; |
fs = FAULT_DOMAIN_S; |
232 |
goto exception_return; |
goto exception_return; |
233 |
} |
} |
234 |
|
*return_addr = (d & 0xfff00000) | (vaddr & 0x000fffff); |
235 |
ap = (d >> 10) & 3; |
ap = (d >> 10) & 3; |
236 |
access = arm_check_access(cpu, ap, dav, user); |
access = arm_check_access(cpu, ap, dav, user); |
237 |
if (access > writeflag) |
if (access > writeflag) |
252 |
fatal("{ arm memory fault: vaddr=0x%08x domain=%i dav=%i ap=%i " |
fatal("{ arm memory fault: vaddr=0x%08x domain=%i dav=%i ap=%i " |
253 |
"access=%i user=%i", (int)vaddr, domain, dav, ap, |
"access=%i user=%i", (int)vaddr, domain, dav, ap, |
254 |
access, user); |
access, user); |
255 |
if (d_in_use) |
fatal(" d=0x%08x d2=0x%08x }\n", d, d2); |
|
fatal(" d=0x%08x", d); |
|
|
if (d2_in_use) |
|
|
fatal(" d2=0x%08x", d2); |
|
|
fatal(" }\n"); |
|
256 |
} |
} |
257 |
|
|
258 |
if (instr) |
if (instr) |