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dpavlin |
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/* |
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* Copyright (C) 2005 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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dpavlin |
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* $Id: cpu_sparc.c,v 1.11 2005/12/11 21:34:43 debug Exp $ |
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dpavlin |
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* |
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* SPARC CPU emulation. |
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*/ |
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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#include <ctype.h> |
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#include "cpu.h" |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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#include "symbol.h" |
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dpavlin |
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dpavlin |
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#define DYNTRANS_DUALMODE_32 |
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#include "tmp_sparc_head.c" |
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dpavlin |
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static char *sparc_regnames[N_SPARC_REG] = SPARC_REG_NAMES; |
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static char *sparc_regbranch_names[N_SPARC_REGBRANCH_TYPES] = |
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SPARC_REGBRANCH_NAMES; |
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static char *sparc_branch_names[N_SPARC_BRANCH_TYPES] = SPARC_BRANCH_NAMES; |
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static char *sparc_alu_names[N_ALU_INSTR_TYPES] = SPARC_ALU_NAMES; |
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static char *sparc_loadstore_names[N_LOADSTORE_TYPES] = SPARC_LOADSTORE_NAMES; |
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dpavlin |
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/* |
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* sparc_cpu_new(): |
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* |
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* Create a new SPARC cpu object. |
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* |
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* Returns 1 on success, 0 if there was no matching SPARC processor with |
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* this cpu_type_name. |
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*/ |
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int sparc_cpu_new(struct cpu *cpu, struct memory *mem, struct machine *machine, |
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int cpu_id, char *cpu_type_name) |
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{ |
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dpavlin |
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int any_cache = 0; |
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int i = 0; |
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struct sparc_cpu_type_def cpu_type_defs[] = SPARC_CPU_TYPE_DEFS; |
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/* Scan the cpu_type_defs list for this cpu type: */ |
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while (cpu_type_defs[i].name != NULL) { |
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if (strcasecmp(cpu_type_defs[i].name, cpu_type_name) == 0) { |
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break; |
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} |
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i++; |
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} |
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if (cpu_type_defs[i].name == NULL) |
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dpavlin |
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return 0; |
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cpu->memory_rw = sparc_memory_rw; |
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dpavlin |
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cpu->cd.sparc.cpu_type = cpu_type_defs[i]; |
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cpu->name = cpu->cd.sparc.cpu_type.name; |
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cpu->byte_order = EMUL_BIG_ENDIAN; |
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cpu->is_32bit = (cpu->cd.sparc.cpu_type.bits == 32)? 1 : 0; |
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dpavlin |
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dpavlin |
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if (cpu->is_32bit) { |
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cpu->update_translation_table = |
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sparc32_update_translation_table; |
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cpu->invalidate_translation_caches = |
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sparc32_invalidate_translation_caches; |
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cpu->invalidate_code_translation = |
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sparc32_invalidate_code_translation; |
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} else { |
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cpu->update_translation_table = sparc_update_translation_table; |
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cpu->invalidate_translation_caches = |
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sparc_invalidate_translation_caches; |
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cpu->invalidate_code_translation = |
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sparc_invalidate_code_translation; |
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} |
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dpavlin |
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/* Only show name and caches etc for CPU nr 0 (in SMP machines): */ |
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if (cpu_id == 0) { |
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debug("%s", cpu->name); |
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dpavlin |
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if (cpu->cd.sparc.cpu_type.icache_shift != 0) |
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any_cache = 1; |
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if (cpu->cd.sparc.cpu_type.dcache_shift != 0) |
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any_cache = 1; |
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if (cpu->cd.sparc.cpu_type.l2cache_shift != 0) |
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any_cache = 1; |
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if (any_cache) { |
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debug(" (I+D = %i+%i KB", (int) |
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(1 << (cpu->cd.sparc.cpu_type.icache_shift-10)), |
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(int)(1<<(cpu->cd.sparc.cpu_type.dcache_shift-10))); |
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if (cpu->cd.sparc.cpu_type.l2cache_shift != 0) { |
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debug(", L2 = %i KB", |
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(int)(1 << (cpu->cd.sparc.cpu_type. |
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l2cache_shift-10))); |
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} |
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debug(")"); |
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} |
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dpavlin |
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} |
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return 1; |
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} |
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/* |
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* sparc_cpu_list_available_types(): |
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* |
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* Print a list of available SPARC CPU types. |
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*/ |
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void sparc_cpu_list_available_types(void) |
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{ |
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dpavlin |
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int i, j; |
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struct sparc_cpu_type_def tdefs[] = SPARC_CPU_TYPE_DEFS; |
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i = 0; |
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while (tdefs[i].name != NULL) { |
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debug("%s", tdefs[i].name); |
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for (j=10 - strlen(tdefs[i].name); j>0; j--) |
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debug(" "); |
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i++; |
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if ((i % 6) == 0 || tdefs[i].name == NULL) |
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debug("\n"); |
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} |
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dpavlin |
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} |
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/* |
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* sparc_cpu_dumpinfo(): |
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*/ |
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void sparc_cpu_dumpinfo(struct cpu *cpu) |
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{ |
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dpavlin |
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debug(", %i-bit\n", cpu->cd.sparc.cpu_type.bits); |
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dpavlin |
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} |
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/* |
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* sparc_cpu_register_dump(): |
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* |
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* Dump cpu registers in a relatively readable format. |
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* |
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* gprs: set to non-zero to dump GPRs and some special-purpose registers. |
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* coprocs: set bit 0..3 to dump registers in coproc 0..3. |
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*/ |
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void sparc_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs) |
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{ |
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char *symbol; |
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dpavlin |
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uint64_t offset; |
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dpavlin |
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int i, x = cpu->cpu_id; |
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int bits32 = cpu->is_32bit; |
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dpavlin |
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if (gprs) { |
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/* Special registers (pc, ...) first: */ |
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symbol = get_symbol_name(&cpu->machine->symbol_context, |
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cpu->pc, &offset); |
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dpavlin |
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debug("cpu%i: pc = 0x", x); |
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dpavlin |
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if (bits32) |
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debug("%08x", (int)cpu->pc); |
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else |
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debug("%016llx", (long long)cpu->pc); |
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debug(" <%s>\n", symbol != NULL? symbol : " no symbol "); |
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dpavlin |
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if (bits32) { |
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for (i=0; i<N_SPARC_REG; i++) { |
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if ((i & 3) == 0) |
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debug("cpu%i: ", x); |
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/* Skip the zero register: */ |
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if (i==0) { |
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debug(" "); |
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continue; |
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} |
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debug("%s=", sparc_regnames[i]); |
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debug("0x%08x", (int) cpu->cd.sparc.r[i]); |
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if ((i & 3) < 3) |
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debug(" "); |
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else |
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debug("\n"); |
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} |
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} else { |
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for (i=0; i<N_SPARC_REG; i++) { |
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int r = ((i >> 1) & 15) | ((i&1) << 4); |
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if ((i & 1) == 0) |
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debug("cpu%i: ", x); |
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/* Skip the zero register: */ |
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if (r==0) { |
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debug(" "); |
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continue; |
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} |
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debug("%s = ", sparc_regnames[r]); |
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debug("0x%016llx", (long long) |
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cpu->cd.sparc.r[r]); |
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if ((i & 1) < 1) |
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debug(" "); |
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else |
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debug("\n"); |
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} |
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} |
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dpavlin |
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} |
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} |
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/* |
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* sparc_cpu_register_match(): |
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*/ |
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void sparc_cpu_register_match(struct machine *m, char *name, |
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int writeflag, uint64_t *valuep, int *match_register) |
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{ |
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int cpunr = 0; |
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/* CPU number: */ |
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/* TODO */ |
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/* Register name: */ |
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if (strcasecmp(name, "pc") == 0) { |
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if (writeflag) { |
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m->cpus[cpunr]->pc = *valuep; |
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} else |
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*valuep = m->cpus[cpunr]->pc; |
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*match_register = 1; |
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} |
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} |
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/* |
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* sparc_cpu_interrupt(): |
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*/ |
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int sparc_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr) |
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{ |
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fatal("sparc_cpu_interrupt(): TODO\n"); |
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return 0; |
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} |
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/* |
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* sparc_cpu_interrupt_ack(): |
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*/ |
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int sparc_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr) |
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{ |
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/* fatal("sparc_cpu_interrupt_ack(): TODO\n"); */ |
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return 0; |
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} |
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/* |
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* sparc_cpu_disassemble_instr(): |
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* |
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* Convert an instruction word into human readable format, for instruction |
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* tracing. |
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* |
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* If running is 1, cpu->pc should be the address of the instruction. |
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* |
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* If running is 0, things that depend on the runtime environment (eg. |
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* register contents) will not be shown, and addr will be used instead of |
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* cpu->pc for relative addresses. |
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*/ |
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int sparc_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr, |
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int running, uint64_t dumpaddr, int bintrans) |
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{ |
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dpavlin |
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uint64_t offset, tmp; |
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dpavlin |
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uint32_t iword; |
289 |
dpavlin |
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int hi2, op2, rd, rs1, rs2, siconst, btype, tmps, no_rd = 0; |
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int asi, no_rs1 = 0, no_rs2 = 0, jmpl = 0, shift_x = 0, cc, p; |
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char *symbol, *mnem; |
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dpavlin |
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if (running) |
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dumpaddr = cpu->pc; |
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symbol = get_symbol_name(&cpu->machine->symbol_context, |
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dumpaddr, &offset); |
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if (symbol != NULL && offset==0) |
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debug("<%s>\n", symbol); |
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301 |
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if (cpu->machine->ncpus > 1 && running) |
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debug("cpu%i: ", cpu->cpu_id); |
303 |
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304 |
dpavlin |
22 |
if (cpu->is_32bit) |
305 |
dpavlin |
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debug("%08x", (int)dumpaddr); |
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else |
307 |
dpavlin |
22 |
debug("%016llx", (long long)dumpaddr); |
308 |
dpavlin |
14 |
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309 |
dpavlin |
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iword = *(uint32_t *)&instr[0]; |
310 |
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iword = BE32_TO_HOST(iword); |
311 |
dpavlin |
14 |
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debug(": %08x\t", iword); |
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/* |
315 |
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* Decode the instruction: |
316 |
dpavlin |
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* |
317 |
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* http://www.cs.unm.edu/~maccabe/classes/341/labman/node9.html is a |
318 |
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* good quick description of SPARC instruction encoding. |
319 |
dpavlin |
14 |
*/ |
320 |
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321 |
dpavlin |
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hi2 = iword >> 30; |
322 |
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rd = (iword >> 25) & 31; |
323 |
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btype = rd & (N_SPARC_BRANCH_TYPES - 1); |
324 |
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rs1 = (iword >> 14) & 31; |
325 |
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asi = (iword >> 5) & 0xff; |
326 |
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rs2 = iword & 31; |
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siconst = (int16_t)((iword & 0x1fff) << 3) >> 3; |
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op2 = (hi2 == 0)? ((iword >> 22) & 7) : ((iword >> 19) & 0x3f); |
329 |
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cc = (iword >> 20) & 3; |
330 |
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p = (iword >> 19) & 1; |
331 |
dpavlin |
14 |
|
332 |
dpavlin |
22 |
switch (hi2) { |
333 |
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334 |
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case 0: switch (op2) { |
335 |
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336 |
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case 0: debug("illtrap\t0x%x", iword & 0x3fffff); |
337 |
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break; |
338 |
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339 |
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case 1: |
340 |
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case 2: |
341 |
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case 3: if (op2 == 3) |
342 |
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debug("%s", sparc_regbranch_names[btype & 7]); |
343 |
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else |
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debug("%s", sparc_branch_names[btype]); |
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if (rd & 16) |
346 |
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debug(",a"); |
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tmps = iword; |
348 |
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switch (op2) { |
349 |
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case 1: tmps <<= 13; |
350 |
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tmps >>= 11; |
351 |
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if (!p) |
352 |
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debug(",pn"); |
353 |
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debug("\t%%%s,", cc==0 ? "icc" : |
354 |
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(cc==2 ? "xcc" : "UNKNOWN")); |
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break; |
356 |
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case 2: tmps <<= 10; |
357 |
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tmps >>= 8; |
358 |
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debug("\t"); |
359 |
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break; |
360 |
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case 3: if (btype & 8) |
361 |
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debug("(INVALID)"); |
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if (!p) |
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debug(",pn"); |
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debug("\t%%%s,", sparc_regnames[rs1]); |
365 |
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tmps = ((iword & 0x300000) >> 6) |
366 |
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| (iword & 0x3fff); |
367 |
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tmps <<= 16; |
368 |
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tmps >>= 14; |
369 |
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break; |
370 |
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} |
371 |
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tmp = (int64_t)(int32_t)tmps; |
372 |
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tmp += dumpaddr; |
373 |
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debug("0x%llx", (long long)tmp); |
374 |
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symbol = get_symbol_name(&cpu->machine-> |
375 |
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symbol_context, tmp, &offset); |
376 |
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if (symbol != NULL) |
377 |
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debug(" \t<%s>", symbol); |
378 |
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break; |
379 |
|
|
|
380 |
|
|
case 4: if (rd == 0) { |
381 |
|
|
debug("nop"); |
382 |
|
|
break; |
383 |
|
|
} |
384 |
|
|
debug("sethi\t%%hi(0x%x),", (iword & 0x3fffff) << 10); |
385 |
|
|
debug("%%%s", sparc_regnames[rd]); |
386 |
|
|
break; |
387 |
|
|
|
388 |
|
|
default:debug("UNIMPLEMENTED hi2=%i, op2=0x%x", hi2, op2); |
389 |
|
|
} |
390 |
|
|
break; |
391 |
|
|
|
392 |
|
|
case 1: tmp = (int32_t)iword << 2; |
393 |
|
|
tmp += dumpaddr; |
394 |
|
|
debug("call\t0x%llx", (long long)tmp); |
395 |
|
|
symbol = get_symbol_name(&cpu->machine->symbol_context, |
396 |
|
|
tmp, &offset); |
397 |
|
|
if (symbol != NULL) |
398 |
|
|
debug(" \t<%s>", symbol); |
399 |
|
|
break; |
400 |
|
|
|
401 |
|
|
case 2: mnem = sparc_alu_names[op2]; |
402 |
|
|
switch (op2) { |
403 |
|
|
case 0: /* add */ |
404 |
|
|
if (rd == rs1 && (iword & 0x3fff) == 0x2001) { |
405 |
|
|
mnem = "inc"; |
406 |
|
|
no_rs1 = no_rs2 = 1; |
407 |
|
|
} |
408 |
|
|
break; |
409 |
|
|
case 2: /* or */ |
410 |
|
|
if (rs1 == 0) { |
411 |
|
|
mnem = "mov"; |
412 |
|
|
no_rs1 = 1; |
413 |
|
|
} |
414 |
|
|
break; |
415 |
|
|
case 4: /* sub */ |
416 |
|
|
if (rd == rs1 && (iword & 0x3fff) == 0x2001) { |
417 |
|
|
mnem = "dec"; |
418 |
|
|
no_rs1 = no_rs2 = 1; |
419 |
|
|
} |
420 |
|
|
break; |
421 |
|
|
case 20:/* subcc */ |
422 |
|
|
if (rd == 0) { |
423 |
|
|
mnem = "cmp"; |
424 |
|
|
no_rd = 1; |
425 |
|
|
} |
426 |
|
|
break; |
427 |
|
|
case 37:/* sll */ |
428 |
|
|
case 38:/* srl */ |
429 |
|
|
case 39:/* sra */ |
430 |
|
|
if (siconst & 0x1000) { |
431 |
|
|
siconst &= 0x3f; |
432 |
|
|
shift_x = 1; |
433 |
|
|
} else |
434 |
|
|
siconst &= 0x1f; |
435 |
|
|
break; |
436 |
|
|
case 43:/* ? */ |
437 |
|
|
if (iword == 0x81580000) { |
438 |
|
|
mnem = "flushw"; |
439 |
|
|
no_rs1 = no_rs2 = no_rd = 1; |
440 |
|
|
} |
441 |
|
|
break; |
442 |
|
|
case 49:/* ? */ |
443 |
|
|
if (iword == 0x83880000) { |
444 |
|
|
mnem = "restored"; |
445 |
|
|
no_rs1 = no_rs2 = no_rd = 1; |
446 |
|
|
} |
447 |
|
|
break; |
448 |
|
|
case 56:/* jmpl */ |
449 |
|
|
jmpl = 1; |
450 |
|
|
if (iword == 0x81c7e008) { |
451 |
|
|
mnem = "ret"; |
452 |
|
|
no_rs1 = no_rs2 = no_rd = 1; |
453 |
|
|
} |
454 |
|
|
if (iword == 0x81c3e008) { |
455 |
|
|
mnem = "retl"; |
456 |
|
|
no_rs1 = no_rs2 = no_rd = 1; |
457 |
|
|
} |
458 |
|
|
break; |
459 |
|
|
case 61:/* restore */ |
460 |
|
|
if (iword == 0x81e80000) |
461 |
|
|
no_rs1 = no_rs2 = no_rd = 1; |
462 |
|
|
break; |
463 |
|
|
case 62:if (iword == 0x83f00000) { |
464 |
|
|
mnem = "retry"; |
465 |
|
|
no_rs1 = no_rs2 = no_rd = 1; |
466 |
|
|
} |
467 |
|
|
break; |
468 |
|
|
} |
469 |
|
|
debug("%s", mnem); |
470 |
|
|
if (shift_x) |
471 |
|
|
debug("x"); |
472 |
|
|
debug("\t"); |
473 |
|
|
if (!no_rs1) |
474 |
|
|
debug("%%%s", sparc_regnames[rs1]); |
475 |
|
|
if (!no_rs1 && !no_rs2) { |
476 |
|
|
if (jmpl) |
477 |
|
|
debug("+"); |
478 |
|
|
else |
479 |
|
|
debug(","); |
480 |
|
|
} |
481 |
|
|
if (!no_rs2) { |
482 |
|
|
if ((iword >> 13) & 1) { |
483 |
|
|
if (siconst >= -9 && siconst <= 9) |
484 |
|
|
debug("%i", siconst); |
485 |
|
|
else |
486 |
|
|
debug("0x%x", siconst); |
487 |
|
|
} else { |
488 |
|
|
debug("%%%s", sparc_regnames[rs2]); |
489 |
|
|
} |
490 |
|
|
} |
491 |
|
|
if ((!no_rs1 || !no_rs2) && !no_rd) |
492 |
|
|
debug(","); |
493 |
|
|
if (!no_rd) |
494 |
|
|
debug("%%%s", sparc_regnames[rd]); |
495 |
|
|
break; |
496 |
|
|
|
497 |
|
|
case 3: debug("%s\t", sparc_loadstore_names[op2]); |
498 |
|
|
if (op2 & 4) |
499 |
|
|
debug("%%%s,", sparc_regnames[rd]); |
500 |
|
|
debug("[%%%s", sparc_regnames[rs1]); |
501 |
|
|
if ((iword >> 13) & 1) { |
502 |
|
|
if (siconst > 0) |
503 |
|
|
debug("+"); |
504 |
|
|
if (siconst != 0) |
505 |
|
|
debug("%i", siconst); |
506 |
|
|
} else { |
507 |
|
|
if (rs2 != 0) |
508 |
|
|
debug("+%%%s", sparc_regnames[rs2]); |
509 |
|
|
} |
510 |
|
|
debug("]"); |
511 |
|
|
if (asi != 0) |
512 |
|
|
debug("(%i)", asi); |
513 |
|
|
if (!(op2 & 4)) |
514 |
|
|
debug(",%%%s", sparc_regnames[rd]); |
515 |
|
|
break; |
516 |
dpavlin |
14 |
} |
517 |
|
|
|
518 |
|
|
debug("\n"); |
519 |
|
|
return sizeof(iword); |
520 |
|
|
} |
521 |
|
|
|
522 |
|
|
|
523 |
|
|
#include "tmp_sparc_tail.c" |
524 |
|
|
|