--- trunk/src/cpus/cpu_dyntrans.c	2007/10/08 16:21:06	33
+++ trunk/src/cpus/cpu_dyntrans.c	2007/10/08 16:21:17	34
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2005-2006  Anders Gavare.  All rights reserved.
+ *  Copyright (C) 2005-2007  Anders Gavare.  All rights reserved.
  *
  *  Redistribution and use in source and binary forms, with or without
  *  modification, are permitted provided that the following conditions are met:
@@ -25,7 +25,7 @@
  *  SUCH DAMAGE.
  *
  *
- *  $Id: cpu_dyntrans.c,v 1.132 2006/10/27 13:12:20 debug Exp $
+ *  $Id: cpu_dyntrans.c,v 1.142 2007/02/11 10:47:31 debug Exp $
  *
  *  Common dyntrans routines. Included from cpu_*.c.
  */
@@ -265,10 +265,6 @@
 			    any instruction for any ISA:  */
 			unsigned char instr[1 <<
 			    DYNTRANS_INSTR_ALIGNMENT_SHIFT];
-#ifdef DYNTRANS_X86
-			cpu->cd.x86.cursegment = X86_S_CS;
-			cpu->cd.x86.seg_override = 0;
-#endif
 			if (!cpu->memory_rw(cpu, cpu->mem, cached_pc, &instr[0],
 			    sizeof(instr), MEM_READ, CACHE_INSTRUCTION)) {
 				fatal("XXX_run_instr(): could not read "
@@ -350,7 +346,7 @@
 		}
 	} else {
 		/*  Execute multiple instructions:  */
-		int n = 0;
+		n_instrs = 0;
 		for (;;) {
 			struct DYNTRANS_IC *ic;
 
@@ -362,13 +358,18 @@
 
 			I; I; I; I; I;   I; I; I; I; I;
 
-			n += 60;
+			I; I; I; I; I;   I; I; I; I; I;
+			I; I; I; I; I;   I; I; I; I; I;
+			I; I; I; I; I;   I; I; I; I; I;
+			I; I; I; I; I;   I; I; I; I; I;
+			I; I; I; I; I;   I; I; I; I; I;
+
+			I; I; I; I; I;   I; I; I; I; I;
 
-			if (n + cpu->n_translated_instrs >=
-			    N_SAFE_DYNTRANS_LIMIT)
+			cpu->n_translated_instrs += 120;
+			if (cpu->n_translated_instrs >= N_SAFE_DYNTRANS_LIMIT)
 				break;
 		}
-		n_instrs = n;
 	}
 
 	n_instrs += cpu->n_translated_instrs;
@@ -411,12 +412,14 @@
 /*  Not yet.  TODO  */
 			if (cpu->machine->emulated_hz > 0) {
 				if (cpu->cd.mips.compare_interrupts_pending > 0)
-					cpu_interrupt(cpu, 7);
+					INTERRUPT_ASSERT(
+					    cpu->cd.mips.irq_compare);
 			} else
 #endif
 			{
 				if (diff1 > 0 && diff2 <= 0)
-					cpu_interrupt(cpu, 7);
+					INTERRUPT_ASSERT(
+					    cpu->cd.mips.irq_compare);
 			}
 		}
 	}
@@ -486,7 +489,7 @@
 	 */
 	for (x=0; x<n_args_to_print; x++) {
 		int64_t d;
-#if defined(DYNTRANS_X86) || defined(DYNTRANS_TRANSPUTER)
+#if defined(DYNTRANS_TRANSPUTER)
 		d = 0;		/*  TODO  */
 #else
 		/*  Args in registers:  */
@@ -502,18 +505,6 @@
 			they go downwards, ie. 22,23 and so on  */
 		    r[24
 #endif
-#ifdef DYNTRANS_AVR32
-		    r[0		/*  TODO  */
-#endif
-#ifdef DYNTRANS_HPPA
-		    r[0		/*  TODO  */
-#endif
-#ifdef DYNTRANS_I960
-		    r[0		/*  TODO  */
-#endif
-#ifdef DYNTRANS_IA64
-		    r[0		/*  TODO  */
-#endif
 #ifdef DYNTRANS_M68K
 		    d[0		/*  TODO  */
 #endif
@@ -574,6 +565,8 @@
 { 
 	struct DYNTRANS_TC_PHYSPAGE *ppp;
 
+	native_commit(cpu);
+
 	ppp = (struct DYNTRANS_TC_PHYSPAGE *)(cpu->translation_cache
 	    + cpu->translation_cache_cur_ofs);
 
@@ -685,9 +678,10 @@
 			}
 #else
 			x1 = (cached_pc >> (64-DYNTRANS_L1N)) & mask1;
-			x2 = (cached_pc >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
-			x3 = (cached_pc >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N))
-			    & mask3;
+			x2 = (cached_pc >> (64-DYNTRANS_L1N-DYNTRANS_L2N))
+			    & mask2;
+			x3 = (cached_pc >> (64-DYNTRANS_L1N-DYNTRANS_L2N
+			    - DYNTRANS_L3N)) & mask3;
 			l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1];
 			l3 = l2->l3[x2];
 			if (l3->host_load[x3] != NULL) {
@@ -731,7 +725,7 @@
 		}
 	}
 
-	if (cpu->translation_cache_cur_ofs >= DYNTRANS_CACHE_SIZE) {
+	if (cpu->translation_cache_cur_ofs >= dyntrans_cache_size) {
 #ifdef UNSTABLE_DEVEL
 		fatal("[ dyntrans: resetting the translation cache ]\n");
 #endif
@@ -765,6 +759,7 @@
 		/*  fatal("CREATING page %lli (physaddr 0x%"PRIx64"), table "
 		    "index %i\n", (long long)pagenr, (uint64_t)physaddr,
 		    (int)table_index);  */
+		native_commit(cpu);
 		*physpage_entryp = physpage_ofs =
 		    cpu->translation_cache_cur_ofs;
 
@@ -1254,6 +1249,12 @@
 		physpage_entryp = &(((uint32_t *)cpu->
 		    translation_cache)[table_index]);
 		physpage_ofs = *physpage_entryp;
+
+		/*  Return immediately if there is no code translation
+		    for this page.  */
+		if (physpage_ofs == 0)
+			return;
+
 		prev_ppp = ppp = NULL;
 
 		/*  Traverse the physical page chain:  */
@@ -1271,8 +1272,10 @@
 			physpage_ofs = ppp->next_ofs;
 		}
 
-		if (physpage_ofs == 0)
-			ppp = NULL;
+		/*  If there is no translation, there is no need to go
+		    on and try to remove it from the vph_tlb_entry array:  */
+		if (ppp == NULL)
+			return;
 
 #if 0
 		/*