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/* |
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* Copyright (C) 2005 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: cpu_avr.c,v 1.5 2005/10/22 17:24:20 debug Exp $ |
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* |
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* Atmel AVR (8-bit) CPU emulation. |
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*/ |
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|
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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#include <ctype.h> |
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|
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#include "cpu.h" |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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#include "symbol.h" |
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|
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|
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#define DYNTRANS_32 |
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#include "tmp_avr_head.c" |
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|
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|
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/* |
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* avr_cpu_new(): |
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* |
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* Create a new AVR cpu object. |
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* |
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* Returns 1 on success, 0 if there was no matching AVR processor with |
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* this cpu_type_name. |
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*/ |
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int avr_cpu_new(struct cpu *cpu, struct memory *mem, struct machine *machine, |
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int cpu_id, char *cpu_type_name) |
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{ |
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if (strcasecmp(cpu_type_name, "AVR") != 0) |
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return 0; |
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|
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cpu->memory_rw = avr_memory_rw; |
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cpu->update_translation_table = avr_update_translation_table; |
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cpu->invalidate_translation_caches = |
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avr_invalidate_translation_caches; |
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cpu->invalidate_code_translation = avr_invalidate_code_translation; |
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cpu->is_32bit = 1; |
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|
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cpu->byte_order = EMUL_LITTLE_ENDIAN; |
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|
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cpu->cd.avr.pc_mask = 0xffff; |
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|
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/* Only show name and caches etc for CPU nr 0 (in SMP machines): */ |
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if (cpu_id == 0) { |
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debug("%s", cpu->name); |
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} |
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|
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return 1; |
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} |
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|
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|
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/* |
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* avr_cpu_list_available_types(): |
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* |
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* Print a list of available AVR CPU types. |
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*/ |
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void avr_cpu_list_available_types(void) |
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{ |
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debug("AVR\n"); |
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/* TODO */ |
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} |
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|
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|
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/* |
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* avr_cpu_dumpinfo(): |
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*/ |
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void avr_cpu_dumpinfo(struct cpu *cpu) |
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{ |
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/* TODO */ |
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debug("\n"); |
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} |
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|
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|
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/* |
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* avr_cpu_register_dump(): |
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* |
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* Dump cpu registers in a relatively readable format. |
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* |
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* gprs: set to non-zero to dump GPRs and some special-purpose registers. |
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* coprocs: set bit 0..3 to dump registers in coproc 0..3. |
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*/ |
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void avr_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs) |
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{ |
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char *symbol; |
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uint64_t offset; |
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int i, x = cpu->cpu_id; |
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|
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if (gprs) { |
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/* Special registers (pc, ...) first: */ |
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symbol = get_symbol_name(&cpu->machine->symbol_context, |
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cpu->pc, &offset); |
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|
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debug("cpu%i: sreg = ", x); |
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debug("%c", cpu->cd.avr.sreg & AVR_SREG_I? 'I' : 'i'); |
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debug("%c", cpu->cd.avr.sreg & AVR_SREG_T? 'T' : 't'); |
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debug("%c", cpu->cd.avr.sreg & AVR_SREG_H? 'H' : 'h'); |
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debug("%c", cpu->cd.avr.sreg & AVR_SREG_S? 'S' : 's'); |
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debug("%c", cpu->cd.avr.sreg & AVR_SREG_V? 'V' : 'v'); |
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debug("%c", cpu->cd.avr.sreg & AVR_SREG_N? 'N' : 'n'); |
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debug("%c", cpu->cd.avr.sreg & AVR_SREG_Z? 'Z' : 'z'); |
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debug("%c", cpu->cd.avr.sreg & AVR_SREG_C? 'C' : 'c'); |
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debug(" pc = 0x%04x", x, (int)cpu->pc); |
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debug(" <%s>\n", symbol != NULL? symbol : " no symbol "); |
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|
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for (i=0; i<N_AVR_REGS; i++) { |
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if ((i % 4) == 0) |
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debug("cpu%i:\t", x); |
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debug("r%02i = 0x%02x", i, cpu->cd.avr.r[i]); |
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debug((i % 4) == 3? "\n" : " "); |
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} |
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} |
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|
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debug("cpu%i: nr of instructions: %lli\n", x, |
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(long long)cpu->machine->ncycles); |
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debug("cpu%i: nr of cycles: %lli\n", x, |
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(long long)(cpu->machine->ncycles + cpu->cd.avr.extra_cycles)); |
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} |
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|
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|
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/* |
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* avr_cpu_register_match(): |
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*/ |
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void avr_cpu_register_match(struct machine *m, char *name, |
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int writeflag, uint64_t *valuep, int *match_register) |
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{ |
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int cpunr = 0; |
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|
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/* CPU number: */ |
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/* TODO */ |
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|
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if (strcasecmp(name, "pc") == 0) { |
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if (writeflag) { |
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m->cpus[cpunr]->pc = *valuep; |
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} else |
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*valuep = m->cpus[cpunr]->pc; |
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*match_register = 1; |
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} else if (name[0] == 'r' && isdigit((int)name[1])) { |
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int nr = atoi(name + 1); |
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if (nr >= 0 && nr < N_AVR_REGS) { |
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if (writeflag) |
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m->cpus[cpunr]->cd.avr.r[nr] = *valuep; |
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else |
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*valuep = m->cpus[cpunr]->cd.avr.r[nr]; |
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*match_register = 1; |
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} |
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} |
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} |
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|
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|
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/* |
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* avr_cpu_show_full_statistics(): |
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* |
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* Show detailed statistics on opcode usage on each cpu. |
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*/ |
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void avr_cpu_show_full_statistics(struct machine *m) |
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{ |
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fatal("avr_cpu_show_full_statistics(): TODO\n"); |
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} |
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|
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|
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/* |
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* avr_cpu_tlbdump(): |
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* |
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* Called from the debugger to dump the TLB in a readable format. |
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* x is the cpu number to dump, or -1 to dump all CPUs. |
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* |
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* If rawflag is nonzero, then the TLB contents isn't formated nicely, |
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* just dumped. |
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*/ |
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void avr_cpu_tlbdump(struct machine *m, int x, int rawflag) |
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{ |
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fatal("avr_cpu_tlbdump(): TODO\n"); |
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} |
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|
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|
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/* |
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* avr_cpu_interrupt(): |
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*/ |
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int avr_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr) |
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{ |
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fatal("avr_cpu_interrupt(): TODO\n"); |
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return 0; |
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} |
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|
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|
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/* |
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* avr_cpu_interrupt_ack(): |
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*/ |
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int avr_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr) |
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{ |
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/* fatal("avr_cpu_interrupt_ack(): TODO\n"); */ |
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return 0; |
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} |
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|
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|
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/* Helper functions: */ |
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static void print_two(unsigned char *instr, int *len) |
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{ debug(" %02x %02x", instr[*len], instr[*len+1]); (*len) += 2; } |
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static void print_spaces(int len) { int i; debug(" "); for (i=0; i<15-len/2*6; |
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i++) debug(" "); } |
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|
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|
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/* |
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* avr_cpu_disassemble_instr(): |
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* |
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* Convert an instruction word into human readable format, for instruction |
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* tracing and disassembly. |
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* |
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* If running is 1, cpu->pc should be the address of the instruction. |
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* |
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* If running is 0, things that depend on the runtime environment (eg. |
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* register contents) will not be shown, and addr will be used instead of |
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* cpu->pc for relative addresses. |
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*/ |
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int avr_cpu_disassemble_instr(struct cpu *cpu, unsigned char *ib, |
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int running, uint64_t dumpaddr, int bintrans) |
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{ |
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uint64_t offset; |
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int len = 0, addr, iw, rd, rr, imm; |
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char *symbol; |
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char *sreg_names = SREG_NAMES; |
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|
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if (running) |
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dumpaddr = cpu->pc; |
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|
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symbol = get_symbol_name(&cpu->machine->symbol_context, |
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dumpaddr, &offset); |
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if (symbol != NULL && offset==0) |
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debug("<%s>\n", symbol); |
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|
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if (cpu->machine->ncpus > 1 && running) |
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debug("cpu%i: ", cpu->cpu_id); |
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|
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/* TODO: 22-bit PC */ |
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debug("0x%04x: ", (int)dumpaddr); |
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|
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print_two(ib, &len); |
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iw = (ib[1] << 8) + ib[0]; |
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|
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if ((iw & 0xffff) == 0x0000) { |
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print_spaces(len); |
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debug("nop\n"); |
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} else if ((iw & 0xfc00) == 0x0c00) { |
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print_spaces(len); |
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rd = (iw & 0x1f0) >> 4; |
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rr = ((iw & 0x200) >> 5) | (iw & 0xf); |
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debug("add\tr%i,r%i\n", rd, rr); |
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} else if ((iw & 0xfc00) == 0x1c00) { |
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print_spaces(len); |
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rd = (iw & 0x1f0) >> 4; |
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rr = ((iw & 0x200) >> 5) | (iw & 0xf); |
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debug("adc\tr%i,r%i\n", rd, rr); |
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} else if ((iw & 0xfc00) == 0x2000) { |
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print_spaces(len); |
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rd = (iw & 0x1f0) >> 4; |
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rr = ((iw & 0x200) >> 5) | (iw & 0xf); |
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debug("and\tr%i,r%i\n", rd, rr); |
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} else if ((iw & 0xfc00) == 0x2c00) { |
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print_spaces(len); |
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rd = (iw & 0x1f0) >> 4; |
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rr = ((iw & 0x200) >> 5) | (iw & 0xf); |
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debug("mov\tr%i,r%i\n", rd, rr); |
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} else if ((iw & 0xfe0f) == 0x8000) { |
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print_spaces(len); |
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rd = (iw >> 4) & 31; |
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debug("ld\tr%i,Z\n", rd); |
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} else if ((iw & 0xfe0f) == 0x8008) { |
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print_spaces(len); |
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rd = (iw >> 4) & 31; |
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debug("ld\tr%i,Y\n", rd); |
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} else if ((iw & 0xfe0f) == 0x900c) { |
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print_spaces(len); |
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rd = (iw >> 4) & 31; |
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debug("ld\tr%i,X\n", rd); |
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} else if ((iw & 0xfc0f) == 0x900f) { |
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print_spaces(len); |
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rd = (iw >> 4) & 31; |
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debug("%s\tr%i\n", iw & 0x200? "push" : "pop", rd); |
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} else if ((iw & 0xfe0f) == 0x9200) { |
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print_two(ib, &len); |
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addr = (ib[3] << 8) + ib[2]; |
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print_spaces(len); |
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debug("sts\t0x%x,r%i\n", addr, (iw & 0x1f0) >> 4); |
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} else if ((iw & 0xfe0f) == 0x9402) { |
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print_spaces(len); |
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rd = (iw >> 4) & 31; |
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debug("swap\tr%i\n", rd); |
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} else if ((iw & 0xff0f) == 0x9408) { |
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print_spaces(len); |
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rd = (iw >> 4) & 7; |
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debug("%s%c\n", iw & 0x80? "cl" : "se", sreg_names[rd]); |
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} else if ((iw & 0xffef) == 0x9508) { |
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/* ret and reti */ |
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print_spaces(len); |
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debug("ret%s\n", (iw & 0x10)? "i" : ""); |
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} else if ((iw & 0xffff) == 0x9588) { |
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print_spaces(len); |
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debug("sleep\n"); |
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} else if ((iw & 0xffff) == 0x95a8) { |
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print_spaces(len); |
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debug("wdr\n"); |
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} else if ((iw & 0xff00) == 0x9600) { |
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print_spaces(len); |
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imm = ((iw & 0xc0) >> 2) | (iw & 0xf); |
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rd = ((iw >> 4) & 3) * 2 + 24; |
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debug("adiw\tr%i:r%i,0x%x\n", rd, rd+1, imm); |
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} else if ((iw & 0xe000) == 0xc000) { |
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print_spaces(len); |
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addr = (int16_t)((iw & 0xfff) << 4); |
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addr = (addr >> 3) + dumpaddr + 2; |
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debug("%s\t0x%x\n", iw & 0x1000? "rcall" : "rjmp", addr); |
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} else if ((iw & 0xf000) == 0xe000) { |
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print_spaces(len); |
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rd = ((iw >> 4) & 0xf) + 16; |
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imm = ((iw >> 4) & 0xf0) | (iw & 0xf); |
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debug("ldi\tr%i,0x%x\n", rd, imm); |
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} else { |
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print_spaces(len); |
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debug("UNIMPLEMENTED 0x%04x\n", iw); |
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} |
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|
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return len; |
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} |
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|
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|
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#include "tmp_avr_tail.c" |
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|