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/* |
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* Cisco router simulation platform. |
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* Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr) |
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* |
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* MIPS64 JIT compiler. |
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*/ |
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#ifndef __MIPS64_JIT_H__ |
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#define __MIPS64_JIT_H__ |
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#include "utils.h" |
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#include "sbox.h" |
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/* Size of executable page area (in Mb) */ |
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#ifndef __CYGWIN__ |
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#define MIPS_EXEC_AREA_SIZE 64 |
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#else |
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#define MIPS_EXEC_AREA_SIZE 16 |
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#endif |
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/* Buffer size for JIT code generation */ |
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#define MIPS_JIT_BUFSIZE 32768 |
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/* Maximum number of X86 chunks */ |
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#define MIPS_JIT_MAX_CHUNKS 32 |
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/* Size of hash for PC lookup */ |
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#define MIPS_JIT_PC_HASH_BITS 16 |
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#define MIPS_JIT_PC_HASH_MASK ((1 << MIPS_JIT_PC_HASH_BITS) - 1) |
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#define MIPS_JIT_PC_HASH_SIZE (1 << MIPS_JIT_PC_HASH_BITS) |
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/* Instruction jump patch */ |
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struct mips64_insn_patch { |
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u_char *jit_insn; |
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m_uint64_t mips_pc; |
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}; |
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/* Instruction patch table */ |
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#define MIPS64_INSN_PATCH_TABLE_SIZE 32 |
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struct mips64_jit_patch_table { |
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struct mips64_insn_patch patches[MIPS64_INSN_PATCH_TABLE_SIZE]; |
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u_int cur_patch; |
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struct mips64_jit_patch_table *next; |
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}; |
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/* MIPS64 translated code block */ |
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struct mips64_jit_tcb { |
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m_uint64_t start_pc; |
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u_char **jit_insn_ptr; |
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m_uint64_t acc_count; |
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mips_insn_t *mips_code; |
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u_int mips_trans_pos; |
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u_int jit_chunk_pos; |
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u_char *jit_ptr; |
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insn_exec_page_t *jit_buffer; |
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insn_exec_page_t *jit_chunks[MIPS_JIT_MAX_CHUNKS]; |
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struct mips64_jit_patch_table *patch_table; |
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mips64_jit_tcb_t *prev,*next; |
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#if DEBUG_BLOCK_TIMESTAMP |
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m_uint64_t tm_first_use,tm_last_use; |
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#endif |
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}; |
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/* MIPS instruction recognition */ |
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struct mips64_insn_tag { |
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int (*emit)(cpu_mips_t *cpu,mips64_jit_tcb_t *,mips_insn_t); |
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m_uint32_t mask,value; |
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int delay_slot; |
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}; |
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/* MIPS jump instruction (for block scan) */ |
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struct mips64_insn_jump { |
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char *name; |
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m_uint32_t mask,value; |
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int offset_bits; |
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int relative; |
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}; |
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/* Get the JIT instruction pointer in a translated block */ |
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static forced_inline |
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u_char *mips64_jit_tcb_get_host_ptr(mips64_jit_tcb_t *b,m_uint64_t vaddr) |
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{ |
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m_uint32_t offset; |
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offset = ((m_uint32_t)vaddr & MIPS_MIN_PAGE_IMASK) >> 2; |
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return(b->jit_insn_ptr[offset]); |
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} |
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/* Check if the specified address belongs to the specified block */ |
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static forced_inline |
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int mips64_jit_tcb_local_addr(mips64_jit_tcb_t *block,m_uint64_t vaddr, |
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u_char **jit_addr) |
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{ |
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if ((vaddr & MIPS_MIN_PAGE_MASK) == block->start_pc) { |
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*jit_addr = mips64_jit_tcb_get_host_ptr(block,vaddr); |
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return(1); |
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} |
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return(0); |
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} |
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/* Check if PC register matches the compiled block virtual address */ |
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static forced_inline |
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int mips64_jit_tcb_match(cpu_mips_t *cpu,mips64_jit_tcb_t *block) |
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{ |
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m_uint64_t vpage; |
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vpage = cpu->pc & ~(m_uint64_t)MIPS_MIN_PAGE_IMASK; |
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return(block->start_pc == vpage); |
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} |
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/* Compute the hash index for the specified PC value */ |
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static forced_inline m_uint32_t mips64_jit_get_pc_hash(m_uint64_t pc) |
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{ |
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m_uint32_t page_hash; |
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page_hash = sbox_u32(pc >> MIPS_MIN_PAGE_SHIFT); |
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return((page_hash ^ (page_hash >> 12)) & MIPS_JIT_PC_HASH_MASK); |
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} |
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/* Check if there are pending IRQ */ |
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extern void mips64_check_pending_irq(mips64_jit_tcb_t *b); |
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/* Initialize instruction lookup table */ |
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void mips64_jit_create_ilt(void); |
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/* Initialize the JIT structure */ |
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int mips64_jit_init(cpu_mips_t *cpu); |
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/* Flush the JIT */ |
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u_int mips64_jit_flush(cpu_mips_t *cpu,u_int threshold); |
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/* Shutdown the JIT */ |
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void mips64_jit_shutdown(cpu_mips_t *cpu); |
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/* Check if an instruction is in a delay slot or not */ |
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int mips64_jit_is_delay_slot(mips64_jit_tcb_t *b,m_uint64_t pc); |
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/* Fetch a MIPS instruction and emit corresponding x86 translated code */ |
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struct mips64_insn_tag *mips64_jit_fetch_and_emit(cpu_mips_t *cpu, |
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mips64_jit_tcb_t *block, |
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int delay_slot); |
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/* Record a patch to apply in a compiled block */ |
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int mips64_jit_tcb_record_patch(mips64_jit_tcb_t *block,u_char *x86_ptr, |
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m_uint64_t vaddr); |
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/* Free an instruction block */ |
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void mips64_jit_tcb_free(cpu_mips_t *cpu,mips64_jit_tcb_t *block, |
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int list_removal); |
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/* Execute compiled MIPS code */ |
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void *mips64_jit_run_cpu(cpu_gen_t *cpu); |
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/* Set the Pointer Counter (PC) register */ |
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void mips64_set_pc(mips64_jit_tcb_t *b,m_uint64_t new_pc); |
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/* Set the Return Address (RA) register */ |
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void mips64_set_ra(mips64_jit_tcb_t *b,m_uint64_t ret_pc); |
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/* Single-step operation */ |
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void mips64_emit_single_step(mips64_jit_tcb_t *b,mips_insn_t insn); |
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/* Virtual Breakpoint */ |
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void mips64_emit_breakpoint(mips64_jit_tcb_t *b); |
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/* Emit unhandled instruction code */ |
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int mips64_emit_invalid_delay_slot(mips64_jit_tcb_t *b); |
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/* |
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* Increment count register and trigger the timer IRQ if value in compare |
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* register is the same. |
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*/ |
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void mips64_inc_cp0_count_reg(mips64_jit_tcb_t *b); |
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/* Increment the number of executed instructions (performance debugging) */ |
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void mips64_inc_perf_counter(mips64_jit_tcb_t *b); |
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#endif |