30 |
#define DEBUG_BCR_REGS 0 |
#define DEBUG_BCR_REGS 0 |
31 |
#define DEBUG_PCI_REGS 0 |
#define DEBUG_PCI_REGS 0 |
32 |
#define DEBUG_ACCESS 0 |
#define DEBUG_ACCESS 0 |
33 |
#define DEBUG_TRANSMIT 0 |
#define DEBUG_TRANSMIT 1 |
34 |
#define DEBUG_RECEIVE 0 |
#define DEBUG_RECEIVE 1 |
35 |
#define DEBUG_UNKNOWN 0 |
#define DEBUG_UNKNOWN 0 |
36 |
|
|
37 |
/* AMD Am79c971 PCI vendor/product codes */ |
/* AMD Am79c971 PCI vendor/product codes */ |
502 |
if (op_type == MTS_READ) { |
if (op_type == MTS_READ) { |
503 |
cpu_log(cpu,d->name,"read access to unknown BCR %d\n",d->rap); |
cpu_log(cpu,d->name,"read access to unknown BCR %d\n",d->rap); |
504 |
} else { |
} else { |
505 |
cpu_log(cpu,d->name,"write access to unknown BCR %d, value=0x%x\n", |
cpu_log(cpu,d->name, |
506 |
|
"write access to unknown BCR %d, value=0x%x\n", |
507 |
d->rap,*data); |
d->rap,*data); |
508 |
} |
} |
509 |
#endif |
#endif |
738 |
* Don't start receive if the RX ring address has not been set |
* Don't start receive if the RX ring address has not been set |
739 |
* and if RX ON is not set. |
* and if RX ON is not set. |
740 |
*/ |
*/ |
741 |
if ((d->rx_start == 0) || !(d->csr[0] & AM79C971_CSR0_TXON)) |
if ((d->rx_start == 0) || !(d->csr[0] & AM79C971_CSR0_RXON)) |
742 |
return(FALSE); |
return(FALSE); |
743 |
|
|
744 |
#if DEBUG_RECEIVE |
#if DEBUG_RECEIVE |
753 |
* for this virtual machine. |
* for this virtual machine. |
754 |
*/ |
*/ |
755 |
hdr = (n_eth_hdr_t *)pkt; |
hdr = (n_eth_hdr_t *)pkt; |
756 |
|
|
757 |
if (am79c971_handle_mac_addr(d,pkt)) |
if (am79c971_handle_mac_addr(d,pkt)) |
758 |
am79c971_receive_pkt(d,pkt,pkt_len); |
am79c971_receive_pkt(d,pkt,pkt_len); |
759 |
|
|
819 |
struct tx_desc txd0,ctxd,ntxd,*ptxd; |
struct tx_desc txd0,ctxd,ntxd,*ptxd; |
820 |
m_uint32_t tx_start,tx_current; |
m_uint32_t tx_start,tx_current; |
821 |
m_uint32_t clen,tot_len; |
m_uint32_t clen,tot_len; |
822 |
|
|
823 |
if ((d->tx_start == 0) || !(d->csr[0] & AM79C971_CSR0_TXON)) |
if ((d->tx_start == 0) || !(d->csr[0] & AM79C971_CSR0_TXON)) |
824 |
return(FALSE); |
return(FALSE); |
825 |
|
|
827 |
tx_start = tx_current = txdesc_get_current(d); |
tx_start = tx_current = txdesc_get_current(d); |
828 |
ptxd = &txd0; |
ptxd = &txd0; |
829 |
txdesc_read(d,tx_start,ptxd); |
txdesc_read(d,tx_start,ptxd); |
830 |
|
|
831 |
/* If we don't own the first descriptor, we cannot transmit */ |
/* If we don't own the first descriptor, we cannot transmit */ |
832 |
if (!(ptxd->tmd[1] & AM79C971_TMD1_OWN)) |
if (!(ptxd->tmd[1] & AM79C971_TMD1_OWN)) |
833 |
return(FALSE); |
return(FALSE); |
834 |
|
|
835 |
#if DEBUG_TRANSMIT |
#if DEBUG_TRANSMIT |
836 |
AM79C971_LOG(d,"am79c971_handle_txring: 1st desc: " |
AM79C971_LOG(d,"am79c971_handle_txring: 1st desc: " |
837 |
"tmd[0]=0x%x, tmd[1]=0x%x, tmd[2]=0x%x, tmd[3]=0x%x\n", |
"tmd[0]=0x%x, tmd[1]=0x%x, tmd[2]=0x%x, tmd[3]=0x%x\n", |
888 |
AM79C971_LOG(d,"sending packet of %u bytes\n",tot_len); |
AM79C971_LOG(d,"sending packet of %u bytes\n",tot_len); |
889 |
mem_dump(log_file,pkt,tot_len); |
mem_dump(log_file,pkt,tot_len); |
890 |
#endif |
#endif |
891 |
|
/* rewrite ISL header if required */ |
892 |
|
cisco_isl_rewrite(pkt,tot_len); |
893 |
|
|
894 |
/* send it on wire */ |
/* send it on wire */ |
895 |
netio_send(d->nio,pkt,tot_len); |
netio_send(d->nio,pkt,tot_len); |
896 |
} |
} |
1041 |
|
|
1042 |
/* Bind a NIO to an AMD Am79c971 device */ |
/* Bind a NIO to an AMD Am79c971 device */ |
1043 |
int dev_am79c971_set_nio(struct am79c971_data *d,netio_desc_t *nio) |
int dev_am79c971_set_nio(struct am79c971_data *d,netio_desc_t *nio) |
1044 |
{ |
{ |
1045 |
/* check that a NIO is not already bound */ |
/* check that a NIO is not already bound */ |
1046 |
if (d->nio != NULL) |
if (d->nio != NULL) |
1047 |
return(-1); |
return(-1); |