/[dynamips]/upstream/dynamips-0.2.7/dev_gt.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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upstream/dynamips-0.2.6-RC5/dev_gt.c revision 6 by dpavlin, Sat Oct 6 16:09:07 2007 UTC upstream/dynamips-0.2.7-RC1/dev_gt.c revision 7 by dpavlin, Sat Oct 6 16:23:47 2007 UTC
# Line 1  Line 1 
1  /*  /*
2   * Cisco 7200 (Predator) simulation platform.   * Cisco router simulation platform.
3   * Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr)   * Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr)
4   *   *
5   * Galileo GT64010/GT64120A/GT96100A system controller.   * Galileo GT64010/GT64120A/GT96100A system controller.
# Line 18  Line 18 
18    
19  #include "utils.h"  #include "utils.h"
20  #include "net.h"  #include "net.h"
21  #include "mips64.h"  #include "cpu.h"
22    #include "vm.h"
23  #include "dynamips.h"  #include "dynamips.h"
24  #include "memory.h"  #include "memory.h"
25  #include "device.h"  #include "device.h"
# Line 386  static void gt_dma_handle_ctrl(struct gt Line 387  static void gt_dma_handle_ctrl(struct gt
387        *data = swap32(gt_data->dma[ch].reg_name);        *data = swap32(gt_data->dma[ch].reg_name);
388    
389  /* Handle a DMA channel */  /* Handle a DMA channel */
390  static int gt_dma_access(cpu_mips_t *cpu,struct vdevice *dev,  static int gt_dma_access(cpu_gen_t *cpu,struct vdevice *dev,
391                              m_uint32_t offset,u_int op_size,u_int op_type,                           m_uint32_t offset,u_int op_size,u_int op_type,
392                              m_uint64_t *data)                           m_uint64_t *data)
393  {  {
394     struct gt_data *gt_data = dev->priv_data;     struct gt_data *gt_data = dev->priv_data;
395    
# Line 458  static int gt_dma_access(cpu_mips_t *cpu Line 459  static int gt_dma_access(cpu_mips_t *cpu
459  /*  /*
460   * dev_gt64010_access()   * dev_gt64010_access()
461   */   */
462  void *dev_gt64010_access(cpu_mips_t *cpu,struct vdevice *dev,m_uint32_t offset,  void *dev_gt64010_access(cpu_gen_t *cpu,struct vdevice *dev,m_uint32_t offset,
463                           u_int op_size,u_int op_type,m_uint64_t *data)                           u_int op_size,u_int op_type,m_uint64_t *data)
464  {  {
465     struct gt_data *gt_data = dev->priv_data;     struct gt_data *gt_data = dev->priv_data;
# Line 566  void *dev_gt64010_access(cpu_mips_t *cpu Line 567  void *dev_gt64010_access(cpu_mips_t *cpu
567        default:        default:
568           if (op_type == MTS_READ) {           if (op_type == MTS_READ) {
569              cpu_log(cpu,"GT64010","read from addr 0x%x, pc=0x%llx\n",              cpu_log(cpu,"GT64010","read from addr 0x%x, pc=0x%llx\n",
570                      offset,cpu->pc);                      offset,cpu_get_pc(cpu));
571           } else {           } else {
572              cpu_log(cpu,"GT64010","write to addr 0x%x, value=0x%llx, "              cpu_log(cpu,"GT64010","write to addr 0x%x, value=0x%llx, "
573                      "pc=0x%llx\n",offset,*data,cpu->pc);                      "pc=0x%llx\n",offset,*data,cpu_get_pc(cpu));
574           }           }
575  #endif  #endif
576     }     }
# Line 580  void *dev_gt64010_access(cpu_mips_t *cpu Line 581  void *dev_gt64010_access(cpu_mips_t *cpu
581  /*  /*
582   * dev_gt64120_access()   * dev_gt64120_access()
583   */   */
584  void *dev_gt64120_access(cpu_mips_t *cpu,struct vdevice *dev,m_uint32_t offset,  void *dev_gt64120_access(cpu_gen_t *cpu,struct vdevice *dev,m_uint32_t offset,
585                           u_int op_size,u_int op_type,m_uint64_t *data)                           u_int op_size,u_int op_type,m_uint64_t *data)
586  {  {
587     struct gt_data *gt_data = dev->priv_data;     struct gt_data *gt_data = dev->priv_data;
# Line 696  void *dev_gt64120_access(cpu_mips_t *cpu Line 697  void *dev_gt64120_access(cpu_mips_t *cpu
697        default:        default:
698           if (op_type == MTS_READ) {           if (op_type == MTS_READ) {
699              cpu_log(cpu,"GT64120","read from addr 0x%x, pc=0x%llx\n",              cpu_log(cpu,"GT64120","read from addr 0x%x, pc=0x%llx\n",
700                      offset,cpu->pc);                      offset,cpu_get_pc(cpu));
701           } else {           } else {
702              cpu_log(cpu,"GT64120","write to addr 0x%x, value=0x%llx, "              cpu_log(cpu,"GT64120","write to addr 0x%x, value=0x%llx, "
703                      "pc=0x%llx\n",offset,*data,cpu->pc);                      "pc=0x%llx\n",offset,*data,cpu_get_pc(cpu));
704           }           }
705  #endif  #endif
706     }     }
# Line 803  static void gt_mii_write(struct gt_data Line 804  static void gt_mii_write(struct gt_data
804  }  }
805    
806  /* Handle registers of Ethernet ports */  /* Handle registers of Ethernet ports */
807  static int gt_eth_access(cpu_mips_t *cpu,struct vdevice *dev,  static int gt_eth_access(cpu_gen_t *cpu,struct vdevice *dev,
808                           m_uint32_t offset,u_int op_size,u_int op_type,                           m_uint32_t offset,u_int op_size,u_int op_type,
809                           m_uint64_t *data)                           m_uint64_t *data)
810  {  {
# Line 1037  static int gt_eth_access(cpu_mips_t *cpu Line 1038  static int gt_eth_access(cpu_mips_t *cpu
1038           if (op_type == MTS_READ) {           if (op_type == MTS_READ) {
1039              cpu_log(cpu,"GT96100/ETH",              cpu_log(cpu,"GT96100/ETH",
1040                      "read access to unknown register 0x%x, pc=0x%llx\n",                      "read access to unknown register 0x%x, pc=0x%llx\n",
1041                      offset,cpu->pc);                      offset,cpu_get_pc(cpu));
1042           } else {           } else {
1043              cpu_log(cpu,"GT96100/ETH",              cpu_log(cpu,"GT96100/ETH",
1044                      "write access to unknown register 0x%x, value=0x%llx, "                      "write access to unknown register 0x%x, value=0x%llx, "
1045                      "pc=0x%llx\n",offset,*data,cpu->pc);                      "pc=0x%llx\n",offset,*data,cpu_get_pc(cpu));
1046           }           }
1047  #endif  #endif
1048     }     }
# Line 1055  static int gt_eth_access(cpu_mips_t *cpu Line 1056  static int gt_eth_access(cpu_mips_t *cpu
1056  /*  /*
1057   * dev_gt96100_access()   * dev_gt96100_access()
1058   */   */
1059  void *dev_gt96100_access(cpu_mips_t *cpu,struct vdevice *dev,m_uint32_t offset,  void *dev_gt96100_access(cpu_gen_t *cpu,struct vdevice *dev,m_uint32_t offset,
1060                           u_int op_size,u_int op_type,m_uint64_t *data)                           u_int op_size,u_int op_type,m_uint64_t *data)
1061  {  {
1062     struct gt_data *gt_data = dev->priv_data;     struct gt_data *gt_data = dev->priv_data;
# Line 1221  void *dev_gt96100_access(cpu_mips_t *cpu Line 1222  void *dev_gt96100_access(cpu_mips_t *cpu
1222        default:        default:
1223           if (op_type == MTS_READ) {           if (op_type == MTS_READ) {
1224              cpu_log(cpu,"GT96100","read from addr 0x%x, pc=0x%llx\n",              cpu_log(cpu,"GT96100","read from addr 0x%x, pc=0x%llx\n",
1225                      offset,cpu->pc);                      offset,cpu_get_pc(cpu));
1226           } else {           } else {
1227              cpu_log(cpu,"GT96100","write to addr 0x%x, value=0x%llx, "              cpu_log(cpu,"GT96100","write to addr 0x%x, value=0x%llx, "
1228                      "pc=0x%llx\n",offset,*data,cpu->pc);                      "pc=0x%llx\n",offset,*data,cpu_get_pc(cpu));
1229           }           }
1230  #endif  #endif
1231     }     }
# Line 1772  int dev_gt64010_init(vm_instance_t *vm,c Line 1773  int dev_gt64010_init(vm_instance_t *vm,c
1773   *   *
1774   * Read a PCI register.   * Read a PCI register.
1775   */   */
1776  static m_uint32_t pci_gt64120_read(cpu_mips_t *cpu,struct pci_device *dev,  static m_uint32_t pci_gt64120_read(cpu_gen_t *cpu,struct pci_device *dev,
1777                                     int reg)                                     int reg)
1778  {    {  
1779     switch (reg) {     switch (reg) {
# Line 1833  int dev_gt64120_init(vm_instance_t *vm,c Line 1834  int dev_gt64120_init(vm_instance_t *vm,c
1834   *   *
1835   * Read a PCI register.   * Read a PCI register.
1836   */   */
1837  static m_uint32_t pci_gt96100_read(cpu_mips_t *cpu,struct pci_device *dev,  static m_uint32_t pci_gt96100_read(cpu_gen_t *cpu,struct pci_device *dev,
1838                                     int reg)                                     int reg)
1839  {    {  
1840     switch (reg) {     switch (reg) {

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