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/* |
/* |
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* Cisco C7200 (Predator) Simulation Platform. |
* Cisco router simulation platform. |
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* Copyright (C) 2005-2006 Christophe Fillot. All rights reserved. |
* Copyright (C) 2005-2006 Christophe Fillot. All rights reserved. |
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* |
* |
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* PA-MC-8TE1 card. Doesn't work at this time. |
* PA-MC-8TE1 card. Doesn't work at this time. |
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#include <pthread.h> |
#include <pthread.h> |
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#include <assert.h> |
#include <assert.h> |
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#include "mips64.h" |
#include "cpu.h" |
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#include "vm.h" |
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#include "dynamips.h" |
#include "dynamips.h" |
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#include "memory.h" |
#include "memory.h" |
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#include "device.h" |
#include "device.h" |
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/* PA-MC-8TE1 Data */ |
/* PA-MC-8TE1 Data */ |
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struct pa_mc_data { |
struct pa_mc_data { |
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char *name; |
char *name; |
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u_int irq; |
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/* Virtual machine */ |
/* Virtual machine */ |
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vm_instance_t *vm; |
vm_instance_t *vm; |
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m_uint8_t ssram_data[0x20000]; |
m_uint8_t ssram_data[0x20000]; |
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/* PLX9054 */ |
/* PLX9054 */ |
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char *plx_name; |
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vm_obj_t *plx_obj; |
vm_obj_t *plx_obj; |
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/* NetIO descriptor */ |
/* NetIO descriptor */ |
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/* |
/* |
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* dev_ssram_access |
* dev_ssram_access |
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*/ |
*/ |
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static void *dev_ssram_access(cpu_mips_t *cpu,struct vdevice *dev, |
static void *dev_ssram_access(cpu_gen_t *cpu,struct vdevice *dev, |
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m_uint32_t offset,u_int op_size,u_int op_type, |
m_uint32_t offset,u_int op_size,u_int op_type, |
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m_uint64_t *data) |
m_uint64_t *data) |
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{ |
{ |
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if (op_type == MTS_READ) { |
if (op_type == MTS_READ) { |
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cpu_log(cpu,d->name, |
cpu_log(cpu,d->name, |
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"read access to offset = 0x%x, pc = 0x%llx (size=%u)\n", |
"read access to offset = 0x%x, pc = 0x%llx (size=%u)\n", |
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offset,cpu->pc,op_size); |
offset,cpu_get_pc(cpu),op_size); |
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} else { |
} else { |
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cpu_log(cpu,d->name,"write access to vaddr = 0x%x, pc = 0x%llx, " |
cpu_log(cpu,d->name,"write access to vaddr = 0x%x, pc = 0x%llx, " |
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"val = 0x%llx (size=%u)\n",offset,cpu->pc,*data,op_size); |
"val = 0x%llx (size=%u)\n", |
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offset,cpu_get_pc(cpu),*data,op_size); |
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} |
} |
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#endif |
#endif |
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printf("DOORBELL: 0x%x\n",val); |
printf("DOORBELL: 0x%x\n",val); |
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/* Trigger interrupt */ |
/* Trigger interrupt */ |
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vm_set_irq(pa_data->vm,2); |
//vm_set_irq(pa_data->vm,pa_data->irq); |
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vm_set_irq(pa_data->vm,3); |
vm_set_irq(pa_data->vm,3); |
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} |
} |
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/* |
/* |
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* pa_mc8te1_access() |
* pa_mc8te1_access() |
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*/ |
*/ |
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static void *pa_mc8te1_access(cpu_mips_t *cpu,struct vdevice *dev, |
static void *pa_mc8te1_access(cpu_gen_t *cpu,struct vdevice *dev, |
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m_uint32_t offset,u_int op_size,u_int op_type, |
m_uint32_t offset,u_int op_size,u_int op_type, |
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m_uint64_t *data) |
m_uint64_t *data) |
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{ |
{ |
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#if DEBUG_ACCESS |
#if DEBUG_ACCESS |
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if (op_type == MTS_READ) { |
if (op_type == MTS_READ) { |
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cpu_log(cpu,d->name,"read access to offset = 0x%x, pc = 0x%llx\n", |
cpu_log(cpu,d->name,"read access to offset = 0x%x, pc = 0x%llx\n", |
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offset,cpu->pc); |
offset,cpu_get_pc(cpu)); |
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} else { |
} else { |
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cpu_log(cpu,d->name,"write access to vaddr = 0x%x, pc = 0x%llx, " |
cpu_log(cpu,d->name,"write access to vaddr = 0x%x, pc = 0x%llx, " |
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"val = 0x%llx\n",offset,cpu->pc,*data); |
"val = 0x%llx\n",offset,cpu_get_pc(cpu),*data); |
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} |
} |
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#endif |
#endif |
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if (op_type == MTS_READ) { |
if (op_type == MTS_READ) { |
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cpu_log(cpu,d->name, |
cpu_log(cpu,d->name, |
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"read from unknown addr 0x%x, pc=0x%llx (size=%u)\n", |
"read from unknown addr 0x%x, pc=0x%llx (size=%u)\n", |
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offset,cpu->pc,op_size); |
offset,cpu_get_pc(cpu),op_size); |
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} else { |
} else { |
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cpu_log(cpu,d->name, |
cpu_log(cpu,d->name, |
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"write to unknown addr 0x%x, value=0x%llx, " |
"write to unknown addr 0x%x, value=0x%llx, " |
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"pc=0x%llx (size=%u)\n",offset,*data,cpu->pc,op_size); |
"pc=0x%llx (size=%u)\n", |
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offset,*data,cpu_get_pc(cpu),op_size); |
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} |
} |
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#endif |
#endif |
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} |
} |
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/* |
/* |
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* pci_pos_read() |
* pci_pos_read() |
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*/ |
*/ |
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static m_uint32_t pci_pos_read(cpu_mips_t *cpu,struct pci_device *dev,int reg) |
static m_uint32_t pci_pos_read(cpu_gen_t *cpu,struct pci_device *dev,int reg) |
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{ |
{ |
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struct pa_mc_data *d = dev->priv_data; |
struct pa_mc_data *d = dev->priv_data; |
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/* |
/* |
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* pci_pos_write() |
* pci_pos_write() |
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*/ |
*/ |
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static void pci_pos_write(cpu_mips_t *cpu,struct pci_device *dev, |
static void pci_pos_write(cpu_gen_t *cpu,struct pci_device *dev, |
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int reg,m_uint32_t value) |
int reg,m_uint32_t value) |
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{ |
{ |
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struct pa_mc_data *d = dev->priv_data; |
struct pa_mc_data *d = dev->priv_data; |
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memset(d,0,sizeof(*d)); |
memset(d,0,sizeof(*d)); |
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d->name = name; |
d->name = name; |
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d->vm = router->vm; |
d->vm = router->vm; |
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d->irq = c7200_net_irq_for_slot_port(pa_bay,0); |
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/* Set the EEPROM */ |
/* Set the EEPROM */ |
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c7200_pa_set_eeprom(router,pa_bay,cisco_eeprom_find_pa("PA-MC-8TE1")); |
c7200_pa_set_eeprom(router,pa_bay,cisco_eeprom_find_pa("PA-MC-8TE1")); |
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/* Create the PM7380 */ |
/* Create the PM7380 */ |
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d->pci_dev = pci_dev_add(router->pa_bay[pa_bay].pci_map,name, |
d->pci_dev = pci_dev_add(router->pa_bay[pa_bay].pci_map,name, |
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0x11f8, 0x7380, |
0x11f8, 0x7380, |
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0,0,C7200_NETIO_IRQ,d, |
0,0,d->irq,d, |
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NULL,pci_pos_read,pci_pos_write); |
NULL,pci_pos_read,pci_pos_write); |
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/* Initialize SSRAM device */ |
/* Initialize SSRAM device */ |
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d->ssram_dev.handler = dev_ssram_access; |
d->ssram_dev.handler = dev_ssram_access; |
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/* Create the PLX9054 */ |
/* Create the PLX9054 */ |
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d->plx_obj = dev_plx9054_init(d->vm,d->name, |
d->plx_name = dyn_sprintf("%s_plx",name); |
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d->plx_obj = dev_plx9054_init(d->vm,d->plx_name, |
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router->pa_bay[pa_bay].pci_map,1, |
router->pa_bay[pa_bay].pci_map,1, |
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&d->ssram_dev,NULL); |
&d->ssram_dev,NULL); |
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