--- upstream/dynamips-0.2.6-RC4/dev_c7200_pos.c 2007/10/06 16:08:03 5 +++ upstream/dynamips-0.2.7-RC2/dev_c7200_pos.c 2007/10/06 16:24:54 8 @@ -1,6 +1,6 @@ /* - * Cisco C7200 (Predator) Simulation Platform. - * Copyright (C) 2005-2006 Christophe Fillot. All rights reserved. + * Cisco router Simulation Platform. + * Copyright (c) 2005-2007 Christophe Fillot. All rights reserved. * * EEPROM types: * - 0x95: PA-POS-OC3SMI @@ -19,7 +19,8 @@ #include #include -#include "mips64.h" +#include "cpu.h" +#include "vm.h" #include "dynamips.h" #include "memory.h" #include "device.h" @@ -31,9 +32,9 @@ /* Debugging flags */ #define DEBUG_ACCESS 0 -#define DEBUG_UNKNOWN 1 -#define DEBUG_TRANSMIT 0 -#define DEBUG_RECEIVE 0 +#define DEBUG_UNKNOWN 0 +#define DEBUG_TRANSMIT 1 +#define DEBUG_RECEIVE 1 /* PCI vendor/product codes */ #define POS_OC3_PCI_VENDOR_ID 0x10b5 @@ -53,7 +54,6 @@ #define POS_OC3_TXDESC_WRAP 0x40000000 /* Wrap ring */ #define POS_OC3_TXDESC_CONT 0x08000000 /* Packet continues */ #define POS_OC3_TXDESC_LEN_MASK 0x1fff -#define POS_OC3_TXDESC_ADDR_MASK 0x3fffffff /* Buffer address (?) */ /* RX Descriptor */ struct rx_desc { @@ -100,9 +100,9 @@ /* * pos_access() */ -static void *dev_pos_access(cpu_mips_t *cpu,struct vdevice *dev, - m_uint32_t offset,u_int op_size,u_int op_type, - m_uint64_t *data) +static void *dev_pos_access(cpu_gen_t *cpu,struct vdevice *dev, + m_uint32_t offset,u_int op_size,u_int op_type, + m_uint64_t *data) { struct pos_oc3_data *d = dev->priv_data; @@ -112,11 +112,11 @@ #if DEBUG_ACCESS if (op_type == MTS_READ) { cpu_log(cpu,d->name,"read access to offset = 0x%x, pc = 0x%llx\n", - offset,cpu->pc); + offset,cpu_get_pc(cpu)); } else { if (offset != 0x404) cpu_log(cpu,d->name,"write access to vaddr = 0x%x, pc = 0x%llx, " - "val = 0x%llx\n",offset,cpu->pc,*data); + "val = 0x%llx\n",offset,cpu_get_pc(cpu),*data); } #endif @@ -139,11 +139,12 @@ if (op_type == MTS_READ) { cpu_log(cpu,d->name, "read from unknown addr 0x%x, pc=0x%llx (size=%u)\n", - offset,cpu->pc,op_size); + offset,cpu_get_pc(cpu),op_size); } else { cpu_log(cpu,d->name, "write to unknown addr 0x%x, value=0x%llx, " - "pc=0x%llx (size=%u)\n",offset,*data,cpu->pc,op_size); + "pc=0x%llx (size=%u)\n", + offset,*data,cpu_get_pc(cpu),op_size); } #endif } @@ -154,7 +155,7 @@ /* * pos_rx_access() */ -static void *dev_pos_rx_access(cpu_mips_t *cpu,struct vdevice *dev, +static void *dev_pos_rx_access(cpu_gen_t *cpu,struct vdevice *dev, m_uint32_t offset,u_int op_size,u_int op_type, m_uint64_t *data) { @@ -166,10 +167,10 @@ #if DEBUG_ACCESS if (op_type == MTS_READ) { cpu_log(cpu,d->name,"read access to offset = 0x%x, pc = 0x%llx\n", - offset,cpu->pc); + offset,cpu_get_pc(cpu)); } else { cpu_log(cpu,d->name,"write access to vaddr = 0x%x, pc = 0x%llx, " - "val = 0x%llx\n",offset,cpu->pc,*data); + "val = 0x%llx\n",offset,cpu_get_pc(cpu),*data); } #endif @@ -193,11 +194,12 @@ if (op_type == MTS_READ) { cpu_log(cpu,d->rx_name, "read from unknown addr 0x%x, pc=0x%llx (size=%u)\n", - offset,cpu->pc,op_size); + offset,cpu_get_pc(cpu),op_size); } else { cpu_log(cpu,d->rx_name, "write to unknown addr 0x%x, value=0x%llx, " - "pc=0x%llx (size=%u)\n",offset,*data,cpu->pc,op_size); + "pc=0x%llx (size=%u)\n", + offset,*data,cpu_get_pc(cpu),op_size); } #endif } @@ -208,7 +210,7 @@ /* * pos_tx_access() */ -static void *dev_pos_tx_access(cpu_mips_t *cpu,struct vdevice *dev, +static void *dev_pos_tx_access(cpu_gen_t *cpu,struct vdevice *dev, m_uint32_t offset,u_int op_size,u_int op_type, m_uint64_t *data) { @@ -220,10 +222,10 @@ #if DEBUG_ACCESS if (op_type == MTS_READ) { cpu_log(cpu,d->tx_name,"read access to offset = 0x%x, pc = 0x%llx\n", - offset,cpu->pc); + offset,cpu_get_pc(cpu)); } else { cpu_log(cpu,d->tx_name,"write access to vaddr = 0x%x, pc = 0x%llx, " - "val = 0x%llx\n",offset,cpu->pc,*data); + "val = 0x%llx\n",offset,cpu_get_pc(cpu),*data); } #endif @@ -247,11 +249,12 @@ if (op_type == MTS_READ) { cpu_log(cpu,d->tx_name, "read from unknown addr 0x%x, pc=0x%llx (size=%u)\n", - offset,cpu->pc,op_size); + offset,cpu_get_pc(cpu),op_size); } else { cpu_log(cpu,d->tx_name, "write to unknown addr 0x%x, value=0x%llx, " - "pc=0x%llx (size=%u)\n",offset,*data,cpu->pc,op_size); + "pc=0x%llx (size=%u)\n", + offset,*data,cpu_get_pc(cpu),op_size); } #endif } @@ -262,7 +265,7 @@ /* * pos_cs_access() */ -static void *dev_pos_cs_access(cpu_mips_t *cpu,struct vdevice *dev, +static void *dev_pos_cs_access(cpu_gen_t *cpu,struct vdevice *dev, m_uint32_t offset,u_int op_size,u_int op_type, m_uint64_t *data) { @@ -274,10 +277,10 @@ #if DEBUG_ACCESS if (op_type == MTS_READ) { cpu_log(cpu,d->cs_name,"read access to offset = 0x%x, pc = 0x%llx\n", - offset,cpu->pc); + offset,cpu_get_pc(cpu)); } else { cpu_log(cpu,d->cs_name,"write access to vaddr = 0x%x, pc = 0x%llx, " - "val = 0x%llx\n",offset,cpu->pc,*data); + "val = 0x%llx\n",offset,cpu_get_pc(cpu),*data); } #endif @@ -285,8 +288,10 @@ case 0x300000: case 0x300004: case 0x30001c: - if (op_type == MTS_READ) - *data = 0x00000FFF; + if (op_type == MTS_READ) { + *data = 0x00000FFF; + pci_dev_clear_irq(d->vm,d->pci_dev); + } break; case 0x300008: @@ -299,11 +304,12 @@ if (op_type == MTS_READ) { cpu_log(cpu,d->cs_name, "read from unknown addr 0x%x, pc=0x%llx (size=%u)\n", - offset,cpu->pc,op_size); + offset,cpu_get_pc(cpu),op_size); } else { cpu_log(cpu,d->cs_name, "write to unknown addr 0x%x, value=0x%llx, " - "pc=0x%llx (size=%u)\n",offset,*data,cpu->pc,op_size); + "pc=0x%llx (size=%u)\n", + offset,*data,cpu_get_pc(cpu),op_size); } #endif } @@ -413,7 +419,7 @@ /* We have finished if the complete packet has been stored */ if (tot_len == 0) { - rxdc->rdes[0] = cp_len + 4; + rxdc->rdes[0] = (cp_len + 4); if (i != 0) physmem_copy_u32_to_vm(d->vm,d->rx_current,rxdc->rdes[0]); @@ -496,7 +502,8 @@ static int dev_pos_oc3_handle_txring(struct pos_oc3_data *d) { u_char pkt[POS_OC3_MAX_PKT_SIZE],*pkt_ptr; - m_uint32_t tx_start,clen,tot_len,addr; + m_uint32_t clen,tot_len,norm_len; + m_uint32_t tx_start,addr; struct tx_desc txd0,ctxd,*ptxd; int i,done = FALSE; @@ -538,11 +545,9 @@ if (clen != 0) { addr = ptxd->tdes[1]; - /* ugly hack, to allow this to work with SRAM platforms */ - if ((addr & ~POS_OC3_TXDESC_ADDR_MASK) == 0xc0000000) - addr = ptxd->tdes[1] & POS_OC3_TXDESC_ADDR_MASK; - - physmem_copy_from_vm(d->vm,pkt_ptr,addr,clen); + norm_len = normalize_size(clen,4,0); + physmem_copy_from_vm(d->vm,pkt_ptr,addr,norm_len); + mem_bswap32(pkt_ptr,norm_len); } pkt_ptr += clen; @@ -586,7 +591,7 @@ /* * pci_pos_read() */ -static m_uint32_t pci_pos_read(cpu_mips_t *cpu,struct pci_device *dev,int reg) +static m_uint32_t pci_pos_read(cpu_gen_t *cpu,struct pci_device *dev,int reg) { struct pos_oc3_data *d = dev->priv_data; @@ -605,7 +610,7 @@ /* * pci_pos_write() */ -static void pci_pos_write(cpu_mips_t *cpu,struct pci_device *dev, +static void pci_pos_write(cpu_gen_t *cpu,struct pci_device *dev, int reg,m_uint32_t value) { struct pos_oc3_data *d = dev->priv_data; @@ -685,7 +690,9 @@ d->dev.phys_len = 0x10000; d->dev.handler = dev_pos_access; - d->pci_dev = pci_dev_add(pci_bus,name,0,0,3,0,C7200_NETIO_IRQ, + d->pci_dev = pci_dev_add(pci_bus,name,0,0,3,0, + /*C7200_NETIO_IRQ,*/ + c7200_net_irq_for_slot_port(pa_bay,0), d,NULL,pci_pos_read,pci_pos_write); /* Store device info into the router structure */