/[dynamips]/upstream/dynamips-0.2.7-RC2/dev_c7200_iofpga.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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upstream/dynamips-0.2.7-RC1/dev_c7200_iofpga.c revision 7 by dpavlin, Sat Oct 6 16:23:47 2007 UTC upstream/dynamips-0.2.7-RC2/dev_c7200_iofpga.c revision 8 by dpavlin, Sat Oct 6 16:24:54 2007 UTC
# Line 26  Line 26 
26  #include "memory.h"  #include "memory.h"
27  #include "device.h"  #include "device.h"
28  #include "dev_vtty.h"  #include "dev_vtty.h"
29  #include "nmc93c46.h"  #include "nmc93cX6.h"
30  #include "ds1620.h"  #include "ds1620.h"
31  #include "dev_c7200.h"  #include "dev_c7200.h"
32    
# Line 133  struct iofpga_data { Line 133  struct iofpga_data {
133  #define IOFPGA_UNLOCK(d) pthread_mutex_unlock(&(d)->lock)  #define IOFPGA_UNLOCK(d) pthread_mutex_unlock(&(d)->lock)
134    
135  /* CPU EEPROM definition */  /* CPU EEPROM definition */
136  static const struct nmc93c46_eeprom_def eeprom_cpu_def = {  static const struct nmc93cX6_eeprom_def eeprom_cpu_def = {
137     SK1_CLOCK_CPU, CS1_CHIP_SEL_CPU,     SK1_CLOCK_CPU, CS1_CHIP_SEL_CPU,
138     DI1_DATA_IN_CPU, DO1_DATA_OUT_CPU,     DI1_DATA_IN_CPU, DO1_DATA_OUT_CPU,
139  };  };
140    
141  /* Midplane EEPROM definition */  /* Midplane EEPROM definition */
142  static const struct nmc93c46_eeprom_def eeprom_midplane_def = {  static const struct nmc93cX6_eeprom_def eeprom_midplane_def = {
143     SK2_CLOCK_MIDPLANE, CS2_CHIP_SEL_MIDPLANE,     SK2_CLOCK_MIDPLANE, CS2_CHIP_SEL_MIDPLANE,
144     DI2_DATA_IN_MIDPLANE, DO2_DATA_OUT_MIDPLANE,     DI2_DATA_IN_MIDPLANE, DO2_DATA_OUT_MIDPLANE,
145  };  };
146    
147  /* PEM (NPE-B) EEPROM definition */  /* PEM (NPE-B) EEPROM definition */
148  static const struct nmc93c46_eeprom_def eeprom_pem_def = {  static const struct nmc93cX6_eeprom_def eeprom_pem_def = {
149     SK1_CLOCK_PEM, CS1_CHIP_SEL_PEM, DI1_DATA_IN_PEM, DO1_DATA_OUT_PEM,     SK1_CLOCK_PEM, CS1_CHIP_SEL_PEM, DI1_DATA_IN_PEM, DO1_DATA_OUT_PEM,
150  };  };
151    
152  /* IOFPGA manages simultaneously CPU and Midplane EEPROM */  /* IOFPGA manages simultaneously CPU and Midplane EEPROM */
153  static const struct nmc93c46_group eeprom_cpu_midplane = {  static const struct nmc93cX6_group eeprom_cpu_midplane = {
154     2, 0, "CPU and Midplane EEPROM", 0,     EEPROM_TYPE_NMC93C46, 2, 0, "CPU and Midplane EEPROM", 0,
155     { &eeprom_cpu_def, &eeprom_midplane_def },     { &eeprom_cpu_def, &eeprom_midplane_def },
156  };  };
157    
# Line 160  static const struct nmc93c46_group eepro Line 160  static const struct nmc93c46_group eepro
160   * PEM stands for "Power Entry Module":   * PEM stands for "Power Entry Module":
161   * http://www.cisco.com/en/US/products/hw/routers/ps341/products_field_notice09186a00801cb26d.shtml   * http://www.cisco.com/en/US/products/hw/routers/ps341/products_field_notice09186a00801cb26d.shtml
162   */   */
163  static const struct nmc93c46_group eeprom_pem_npeb = {  static const struct nmc93cX6_group eeprom_pem_npeb = {
164     1, 0, "PEM (NPE-B) EEPROM", 0, { &eeprom_pem_def },     EEPROM_TYPE_NMC93C46, 1, 0, "PEM (NPE-B) EEPROM", 0, { &eeprom_pem_def },
165  };  };
166    
167  /* Reset DS1620 */  /* Reset DS1620 */
# Line 454  void *dev_c7200_iofpga_access(cpu_gen_t Line 454  void *dev_c7200_iofpga_access(cpu_gen_t
454        /* CPU/Midplane EEPROMs */        /* CPU/Midplane EEPROMs */
455        case 0x21c:        case 0x21c:
456           if (op_type == MTS_WRITE)           if (op_type == MTS_WRITE)
457              nmc93c46_write(&d->router->sys_eeprom_g1,(u_int)(*data));              nmc93cX6_write(&d->router->sys_eeprom_g1,(u_int)(*data));
458           else           else
459              *data = nmc93c46_read(&d->router->sys_eeprom_g1);              *data = nmc93cX6_read(&d->router->sys_eeprom_g1);
460           break;           break;
461    
462        /* PEM (NPE-B) EEPROM */        /* PEM (NPE-B) EEPROM */
463        case 0x388:        case 0x388:
464            if (op_type == MTS_WRITE)            if (op_type == MTS_WRITE)
465              nmc93c46_write(&d->router->sys_eeprom_g2,(u_int)(*data));              nmc93cX6_write(&d->router->sys_eeprom_g2,(u_int)(*data));
466           else           else
467              *data = nmc93c46_read(&d->router->sys_eeprom_g2);              *data = nmc93cX6_read(&d->router->sys_eeprom_g2);
468           break;           break;
469    
470        /* Watchdog */        /* Watchdog */

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