/[dynamips]/upstream/dynamips-0.2.7-RC2/dev_c2691_iofpga.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Diff of /upstream/dynamips-0.2.7-RC2/dev_c2691_iofpga.c

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upstream/dynamips-0.2.6-RC4/dev_c2691_iofpga.c revision 5 by dpavlin, Sat Oct 6 16:08:03 2007 UTC upstream/dynamips-0.2.7-RC1/dev_c2691_iofpga.c revision 7 by dpavlin, Sat Oct 6 16:23:47 2007 UTC
# Line 13  Line 13 
13  #include <pthread.h>  #include <pthread.h>
14    
15  #include "ptask.h"  #include "ptask.h"
16  #include "mips64.h"  #include "cpu.h"
17    #include "vm.h"
18  #include "dynamips.h"  #include "dynamips.h"
19  #include "memory.h"  #include "memory.h"
20  #include "device.h"  #include "device.h"
# Line 85  static const struct nmc93c46_group eepro Line 86  static const struct nmc93c46_group eepro
86   * dev_c2691_iofpga_access()   * dev_c2691_iofpga_access()
87   */   */
88  static void *  static void *
89  dev_c2691_iofpga_access(cpu_mips_t *cpu,struct vdevice *dev,  dev_c2691_iofpga_access(cpu_gen_t *cpu,struct vdevice *dev,
90                          m_uint32_t offset,u_int op_size,u_int op_type,                          m_uint32_t offset,u_int op_size,u_int op_type,
91                          m_uint64_t *data)                          m_uint64_t *data)
92  {  {
# Line 97  dev_c2691_iofpga_access(cpu_mips_t *cpu, Line 98  dev_c2691_iofpga_access(cpu_mips_t *cpu,
98  #if DEBUG_ACCESS  #if DEBUG_ACCESS
99     if (op_type == MTS_READ) {     if (op_type == MTS_READ) {
100        cpu_log(cpu,"IO_FPGA","reading reg 0x%x at pc=0x%llx (size=%u)\n",        cpu_log(cpu,"IO_FPGA","reading reg 0x%x at pc=0x%llx (size=%u)\n",
101                offset,cpu->pc,op_size);                offset,cpu_get_pc(cpu),op_size);
102     } else {     } else {
103        cpu_log(cpu,"IO_FPGA",        cpu_log(cpu,"IO_FPGA",
104                "writing reg 0x%x at pc=0x%llx, data=0x%llx (size=%u)\n",                "writing reg 0x%x at pc=0x%llx, data=0x%llx (size=%u)\n",
105                offset,cpu->pc,*data,op_size);                offset,cpu_get_pc(cpu),*data,op_size);
106     }     }
107  #endif  #endif
108    
# Line 277  dev_c2691_iofpga_access(cpu_mips_t *cpu, Line 278  dev_c2691_iofpga_access(cpu_mips_t *cpu,
278           if (op_type == MTS_READ) {           if (op_type == MTS_READ) {
279              cpu_log(cpu,"IO_FPGA",              cpu_log(cpu,"IO_FPGA",
280                      "read from unknown addr 0x%x, pc=0x%llx (size=%u)\n",                      "read from unknown addr 0x%x, pc=0x%llx (size=%u)\n",
281                      offset,cpu->pc,op_size);                      offset,cpu_get_pc(cpu),op_size);
282           } else {           } else {
283              cpu_log(cpu,"IO_FPGA",              cpu_log(cpu,"IO_FPGA",
284                      "write to unknown addr 0x%x, value=0x%llx, "                      "write to unknown addr 0x%x, value=0x%llx, "
285                      "pc=0x%llx (size=%u)\n",offset,*data,cpu->pc,op_size);                      "pc=0x%llx (size=%u)\n",
286                        offset,*data,cpu_get_pc(cpu),op_size);
287           }           }
288  #endif  #endif
289     }     }

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