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/* |
/* |
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* Cisco C7200 (Predator) Simulation Platform. |
* Cisco router simulation platform. |
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* Copyright (C) 2005,2006 Christophe Fillot. All rights reserved. |
* Copyright (C) 2005,2006 Christophe Fillot. All rights reserved. |
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* |
* |
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* PA-A1 ATM interface based on TI1570 and PLX 9060-ES. |
* PA-A1 ATM interface based on TI1570 and PLX 9060-ES. |
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#include "crc.h" |
#include "crc.h" |
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#include "atm.h" |
#include "atm.h" |
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#include "mips64.h" |
#include "cpu.h" |
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|
#include "vm.h" |
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#include "dynamips.h" |
#include "dynamips.h" |
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#include "memory.h" |
#include "memory.h" |
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#include "device.h" |
#include "device.h" |
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/* |
/* |
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* dev_pa_a1_access() |
* dev_pa_a1_access() |
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*/ |
*/ |
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void *dev_pa_a1_access(cpu_mips_t *cpu,struct vdevice *dev,m_uint32_t offset, |
void *dev_pa_a1_access(cpu_gen_t *cpu,struct vdevice *dev,m_uint32_t offset, |
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u_int op_size,u_int op_type,m_uint64_t *data) |
u_int op_size,u_int op_type,m_uint64_t *data) |
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{ |
{ |
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struct pa_a1_data *d = dev->priv_data; |
struct pa_a1_data *d = dev->priv_data; |
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#if DEBUG_ACCESS |
#if DEBUG_ACCESS |
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if (op_type == MTS_READ) { |
if (op_type == MTS_READ) { |
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cpu_log(cpu,"TI1570","read access to offset = 0x%x, pc = 0x%llx\n", |
cpu_log(cpu,"TI1570","read access to offset = 0x%x, pc = 0x%llx\n", |
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offset,cpu->pc); |
offset,cpu_get_pc(cpu)); |
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} else { |
} else { |
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cpu_log(cpu,"TI1570","write access to vaddr = 0x%x, pc = 0x%llx, " |
cpu_log(cpu,"TI1570","write access to vaddr = 0x%x, pc = 0x%llx, " |
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"val = 0x%llx\n",offset,cpu->pc,*data); |
"val = 0x%llx\n",offset,cpu_get_pc(cpu),*data); |
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} |
} |
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#endif |
#endif |
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|
|
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#if DEBUG_UNKNOWN |
#if DEBUG_UNKNOWN |
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if (op_type == MTS_READ) { |
if (op_type == MTS_READ) { |
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cpu_log(cpu,d->name,"read from unknown addr 0x%x, pc=0x%llx (size=%u)\n", |
cpu_log(cpu,d->name,"read from unknown addr 0x%x, pc=0x%llx (size=%u)\n", |
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offset,cpu->pc,op_size); |
offset,cpu_get_pc(cpu),op_size); |
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} else { |
} else { |
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cpu_log(cpu,d->name,"write to unknown addr 0x%x, value=0x%llx, " |
cpu_log(cpu,d->name,"write to unknown addr 0x%x, value=0x%llx, " |
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"pc=0x%llx (size=%u)\n",offset,*data,cpu->pc,op_size); |
"pc=0x%llx (size=%u)\n",offset,*data,cpu_get_pc(cpu),op_size); |
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} |
} |
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#endif |
#endif |
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return NULL; |
return NULL; |
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/* |
/* |
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* pci_ti1570_read() |
* pci_ti1570_read() |
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*/ |
*/ |
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static m_uint32_t pci_ti1570_read(cpu_mips_t *cpu,struct pci_device *dev, |
static m_uint32_t pci_ti1570_read(cpu_gen_t *cpu,struct pci_device *dev, |
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int reg) |
int reg) |
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{ |
{ |
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struct pa_a1_data *d = dev->priv_data; |
struct pa_a1_data *d = dev->priv_data; |
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/* |
/* |
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* pci_ti1570_write() |
* pci_ti1570_write() |
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*/ |
*/ |
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static void pci_ti1570_write(cpu_mips_t *cpu,struct pci_device *dev, |
static void pci_ti1570_write(cpu_gen_t *cpu,struct pci_device *dev, |
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int reg,m_uint32_t value) |
int reg,m_uint32_t value) |
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{ |
{ |
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struct pa_a1_data *d = dev->priv_data; |
struct pa_a1_data *d = dev->priv_data; |
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/* |
/* |
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* pci_plx9060es_read() |
* pci_plx9060es_read() |
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*/ |
*/ |
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static m_uint32_t pci_plx9060es_read(cpu_mips_t *cpu,struct pci_device *dev, |
static m_uint32_t pci_plx9060es_read(cpu_gen_t *cpu,struct pci_device *dev, |
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int reg) |
int reg) |
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{ |
{ |
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#if DEBUG_ACCESS |
#if DEBUG_ACCESS |
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/* |
/* |
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* pci_plx9060es_write() |
* pci_plx9060es_write() |
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*/ |
*/ |
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static void pci_plx9060es_write(cpu_mips_t *cpu,struct pci_device *dev, |
static void pci_plx9060es_write(cpu_gen_t *cpu,struct pci_device *dev, |
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int reg,m_uint32_t value) |
int reg,m_uint32_t value) |
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{ |
{ |
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#if DEBUG_ACCESS |
#if DEBUG_ACCESS |