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/* |
/* |
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* Cisco 7200 (Predator) simulation platform. |
* Cisco router simulation platform. |
3 |
* Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr) |
* Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr) |
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* |
* |
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* Galileo GT64010/GT64120A/GT96100A system controller. |
* Galileo GT64010/GT64120A/GT96100A system controller. |
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|
|
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#include "utils.h" |
#include "utils.h" |
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#include "net.h" |
#include "net.h" |
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#include "mips64.h" |
#include "cpu.h" |
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|
#include "vm.h" |
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#include "dynamips.h" |
#include "dynamips.h" |
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#include "memory.h" |
#include "memory.h" |
25 |
#include "device.h" |
#include "device.h" |
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*data = swap32(gt_data->dma[ch].reg_name); |
*data = swap32(gt_data->dma[ch].reg_name); |
388 |
|
|
389 |
/* Handle a DMA channel */ |
/* Handle a DMA channel */ |
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static int gt_dma_access(cpu_mips_t *cpu,struct vdevice *dev, |
static int gt_dma_access(cpu_gen_t *cpu,struct vdevice *dev, |
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m_uint32_t offset,u_int op_size,u_int op_type, |
m_uint32_t offset,u_int op_size,u_int op_type, |
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m_uint64_t *data) |
m_uint64_t *data) |
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{ |
{ |
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struct gt_data *gt_data = dev->priv_data; |
struct gt_data *gt_data = dev->priv_data; |
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|
|
459 |
/* |
/* |
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* dev_gt64010_access() |
* dev_gt64010_access() |
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*/ |
*/ |
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void *dev_gt64010_access(cpu_mips_t *cpu,struct vdevice *dev,m_uint32_t offset, |
void *dev_gt64010_access(cpu_gen_t *cpu,struct vdevice *dev,m_uint32_t offset, |
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u_int op_size,u_int op_type,m_uint64_t *data) |
u_int op_size,u_int op_type,m_uint64_t *data) |
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{ |
{ |
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struct gt_data *gt_data = dev->priv_data; |
struct gt_data *gt_data = dev->priv_data; |
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default: |
default: |
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if (op_type == MTS_READ) { |
if (op_type == MTS_READ) { |
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cpu_log(cpu,"GT64010","read from addr 0x%x, pc=0x%llx\n", |
cpu_log(cpu,"GT64010","read from addr 0x%x, pc=0x%llx\n", |
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offset,cpu->pc); |
offset,cpu_get_pc(cpu)); |
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} else { |
} else { |
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cpu_log(cpu,"GT64010","write to addr 0x%x, value=0x%llx, " |
cpu_log(cpu,"GT64010","write to addr 0x%x, value=0x%llx, " |
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"pc=0x%llx\n",offset,*data,cpu->pc); |
"pc=0x%llx\n",offset,*data,cpu_get_pc(cpu)); |
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} |
} |
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#endif |
#endif |
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} |
} |
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/* |
/* |
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* dev_gt64120_access() |
* dev_gt64120_access() |
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*/ |
*/ |
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void *dev_gt64120_access(cpu_mips_t *cpu,struct vdevice *dev,m_uint32_t offset, |
void *dev_gt64120_access(cpu_gen_t *cpu,struct vdevice *dev,m_uint32_t offset, |
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u_int op_size,u_int op_type,m_uint64_t *data) |
u_int op_size,u_int op_type,m_uint64_t *data) |
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{ |
{ |
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struct gt_data *gt_data = dev->priv_data; |
struct gt_data *gt_data = dev->priv_data; |
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default: |
default: |
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if (op_type == MTS_READ) { |
if (op_type == MTS_READ) { |
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cpu_log(cpu,"GT64120","read from addr 0x%x, pc=0x%llx\n", |
cpu_log(cpu,"GT64120","read from addr 0x%x, pc=0x%llx\n", |
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offset,cpu->pc); |
offset,cpu_get_pc(cpu)); |
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} else { |
} else { |
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cpu_log(cpu,"GT64120","write to addr 0x%x, value=0x%llx, " |
cpu_log(cpu,"GT64120","write to addr 0x%x, value=0x%llx, " |
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"pc=0x%llx\n",offset,*data,cpu->pc); |
"pc=0x%llx\n",offset,*data,cpu_get_pc(cpu)); |
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} |
} |
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#endif |
#endif |
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} |
} |
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} |
} |
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|
|
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/* Handle registers of Ethernet ports */ |
/* Handle registers of Ethernet ports */ |
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static int gt_eth_access(cpu_mips_t *cpu,struct vdevice *dev, |
static int gt_eth_access(cpu_gen_t *cpu,struct vdevice *dev, |
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m_uint32_t offset,u_int op_size,u_int op_type, |
m_uint32_t offset,u_int op_size,u_int op_type, |
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m_uint64_t *data) |
m_uint64_t *data) |
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{ |
{ |
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if (op_type == MTS_READ) { |
if (op_type == MTS_READ) { |
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cpu_log(cpu,"GT96100/ETH", |
cpu_log(cpu,"GT96100/ETH", |
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"read access to unknown register 0x%x, pc=0x%llx\n", |
"read access to unknown register 0x%x, pc=0x%llx\n", |
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offset,cpu->pc); |
offset,cpu_get_pc(cpu)); |
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} else { |
} else { |
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cpu_log(cpu,"GT96100/ETH", |
cpu_log(cpu,"GT96100/ETH", |
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"write access to unknown register 0x%x, value=0x%llx, " |
"write access to unknown register 0x%x, value=0x%llx, " |
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"pc=0x%llx\n",offset,*data,cpu->pc); |
"pc=0x%llx\n",offset,*data,cpu_get_pc(cpu)); |
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} |
} |
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#endif |
#endif |
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} |
} |
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/* |
/* |
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* dev_gt96100_access() |
* dev_gt96100_access() |
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*/ |
*/ |
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void *dev_gt96100_access(cpu_mips_t *cpu,struct vdevice *dev,m_uint32_t offset, |
void *dev_gt96100_access(cpu_gen_t *cpu,struct vdevice *dev,m_uint32_t offset, |
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u_int op_size,u_int op_type,m_uint64_t *data) |
u_int op_size,u_int op_type,m_uint64_t *data) |
1061 |
{ |
{ |
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struct gt_data *gt_data = dev->priv_data; |
struct gt_data *gt_data = dev->priv_data; |
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default: |
default: |
1223 |
if (op_type == MTS_READ) { |
if (op_type == MTS_READ) { |
1224 |
cpu_log(cpu,"GT96100","read from addr 0x%x, pc=0x%llx\n", |
cpu_log(cpu,"GT96100","read from addr 0x%x, pc=0x%llx\n", |
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offset,cpu->pc); |
offset,cpu_get_pc(cpu)); |
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} else { |
} else { |
1227 |
cpu_log(cpu,"GT96100","write to addr 0x%x, value=0x%llx, " |
cpu_log(cpu,"GT96100","write to addr 0x%x, value=0x%llx, " |
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"pc=0x%llx\n",offset,*data,cpu->pc); |
"pc=0x%llx\n",offset,*data,cpu_get_pc(cpu)); |
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} |
} |
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#endif |
#endif |
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} |
} |
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* |
* |
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* Read a PCI register. |
* Read a PCI register. |
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*/ |
*/ |
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static m_uint32_t pci_gt64120_read(cpu_mips_t *cpu,struct pci_device *dev, |
static m_uint32_t pci_gt64120_read(cpu_gen_t *cpu,struct pci_device *dev, |
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int reg) |
int reg) |
1778 |
{ |
{ |
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switch (reg) { |
switch (reg) { |
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* |
* |
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* Read a PCI register. |
* Read a PCI register. |
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*/ |
*/ |
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static m_uint32_t pci_gt96100_read(cpu_mips_t *cpu,struct pci_device *dev, |
static m_uint32_t pci_gt96100_read(cpu_gen_t *cpu,struct pci_device *dev, |
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int reg) |
int reg) |
1839 |
{ |
{ |
1840 |
switch (reg) { |
switch (reg) { |