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/* |
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* Cisco 3745 simulation platform. |
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* Copyright (c) 2006 Christophe Fillot (cf@utc.fr) |
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* |
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* This is very similar to c2691. |
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*/ |
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|
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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#include <unistd.h> |
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#include <sys/types.h> |
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#include <termios.h> |
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#include <fcntl.h> |
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#include <pthread.h> |
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|
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#include "ptask.h" |
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#include "cpu.h" |
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#include "vm.h" |
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#include "dynamips.h" |
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#include "memory.h" |
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#include "device.h" |
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#include "dev_vtty.h" |
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#include "nmc93c46.h" |
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#include "dev_c3745.h" |
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|
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/* Debugging flags */ |
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#define DEBUG_UNKNOWN 1 |
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#define DEBUG_ACCESS 0 |
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|
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/* Definitions for Motherboard EEPROM (0x00) */ |
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#define EEPROM_MB_DOUT 3 |
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#define EEPROM_MB_DIN 2 |
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#define EEPROM_MB_CLK 1 |
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#define EEPROM_MB_CS 0 |
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|
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/* Definitions for I/O board EEPROM (0x01) */ |
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#define EEPROM_IO_DOUT 3 |
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#define EEPROM_IO_DIN 2 |
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#define EEPROM_IO_CLK 1 |
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#define EEPROM_IO_CS 8 |
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|
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/* Definitions for Midplane EEPROM (0x02) */ |
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#define EEPROM_MP_DOUT 3 |
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#define EEPROM_MP_DIN 2 |
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#define EEPROM_MP_CLK 1 |
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#define EEPROM_MP_CS 9 |
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|
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/* Definitions for Network Modules EEPROM */ |
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#define EEPROM_NM_DOUT 7 |
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#define EEPROM_NM_DIN 6 |
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#define EEPROM_NM_CLK 2 |
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#define EEPROM_NM_CS 4 |
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|
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#define C3745_NET_IRQ_CLEARING_DELAY 16 |
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|
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/* IO FPGA structure */ |
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struct iofpga_data { |
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vm_obj_t vm_obj; |
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struct vdevice dev; |
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c3745_t *router; |
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|
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/* |
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* Used to introduce a "delay" before clearing the network interrupt |
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* on 3620/3640 platforms. Added due to a packet loss when using an |
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* Ethernet NM on these platforms. |
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* |
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* Anyway, we should rely on the device information with appropriate IRQ |
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* routing. |
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*/ |
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int net_irq_clearing_count; |
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|
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/* Interrupt mask */ |
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m_uint16_t intr_mask,io_mask2; |
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|
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/* EEPROM select */ |
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u_int eeprom_select; |
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}; |
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|
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/* Motherboard EEPROM definition */ |
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static const struct nmc93c46_eeprom_def eeprom_mb_def = { |
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EEPROM_MB_CLK, EEPROM_MB_CS, |
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EEPROM_MB_DIN, EEPROM_MB_DOUT, |
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}; |
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|
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/* I/O board EEPROM definition */ |
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static const struct nmc93c46_eeprom_def eeprom_io_def = { |
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EEPROM_IO_CLK, EEPROM_IO_CS, |
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EEPROM_IO_DIN, EEPROM_IO_DOUT, |
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}; |
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|
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/* Midplane EEPROM definition */ |
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static const struct nmc93c46_eeprom_def eeprom_mp_def = { |
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EEPROM_MP_CLK, EEPROM_MP_CS, |
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EEPROM_MP_DIN, EEPROM_MP_DOUT, |
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}; |
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|
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/* System EEPROM group */ |
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static const struct nmc93c46_group eeprom_sys_group = { |
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3, 0, "System EEPROM", 0, |
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{ &eeprom_mb_def, &eeprom_io_def, &eeprom_mp_def }, |
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}; |
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|
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/* NM EEPROM definition */ |
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static const struct nmc93c46_eeprom_def eeprom_nm_def = { |
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EEPROM_NM_CLK, EEPROM_NM_CS, |
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EEPROM_NM_DIN, EEPROM_NM_DOUT, |
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}; |
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|
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/* NM EEPROM */ |
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static const struct nmc93c46_group eeprom_nm_group = { |
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1, 0, "NM EEPROM", 0, { &eeprom_nm_def }, |
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}; |
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|
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/* |
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* dev_c3745_iofpga_access() |
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*/ |
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static void * |
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dev_c3745_iofpga_access(cpu_gen_t *cpu,struct vdevice *dev, |
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m_uint32_t offset,u_int op_size,u_int op_type, |
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m_uint64_t *data) |
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{ |
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struct iofpga_data *d = dev->priv_data; |
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u_int slot; |
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|
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if (op_type == MTS_READ) |
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*data = 0x0; |
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|
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#if DEBUG_ACCESS |
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if (op_type == MTS_READ) { |
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cpu_log(cpu,"IO_FPGA","reading reg 0x%x at pc=0x%llx (size=%u)\n", |
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offset,cpu_get_pc(cpu),op_size); |
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} else { |
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cpu_log(cpu,"IO_FPGA", |
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"writing reg 0x%x at pc=0x%llx, data=0x%llx (size=%u)\n", |
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offset,cpu_get_pc(cpu),*data,op_size); |
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} |
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#endif |
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|
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switch(offset) { |
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/* Unknown */ |
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case 0x000000: |
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if (op_type == MTS_READ) |
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*data = 0xFFFF; |
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break; |
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|
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/* Unknown */ |
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case 0x000004: |
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if (op_type == MTS_READ) |
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*data = 0xFFFF; |
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break; |
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|
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/* |
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* CompactFlash. |
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* |
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* Bit 0: Slot0 Compact Flash presence. |
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* Bit 1: System Compact Flash presence. |
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*/ |
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case 0x000012: |
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if (op_type == MTS_READ) { |
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*data = 0xFFFF; |
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|
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/* System Flash ? */ |
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if (cpu->vm->pcmcia_disk_size[0]) |
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*data &= ~0x02; |
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|
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/* Slot0 Flash ? */ |
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if (cpu->vm->pcmcia_disk_size[1]) |
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*data &= ~0x01; |
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} |
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break; |
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|
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/* Suppress the "****TDM FPGA download failed.." message */ |
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case 0x000014: |
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if (op_type == MTS_READ) |
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*data = 0x00FF; |
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break; |
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|
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/* Power supply status */ |
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case 0x00000a: |
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if (op_type == MTS_READ) |
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*data = 0x0000; |
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break; |
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|
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/* Fan status */ |
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case 0x00000c: |
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if (op_type == MTS_READ) |
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*data = 0x0000; |
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break; |
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|
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/* System EEPROMs */ |
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case 0x00000e: |
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if (op_type == MTS_WRITE) |
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nmc93c46_write(&d->router->sys_eeprom_group,(u_int)(*data)); |
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else |
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*data = nmc93c46_read(&d->router->sys_eeprom_group); |
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break; |
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|
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/* |
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* Network interrupt status. |
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* |
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* Bit 0: 0 = GT96100 Ethernet ports. |
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* Bit 8: 0 = AIM slot 0. |
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* Bit 9: 0 = AIM slot 1. |
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*/ |
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case 0x000020: |
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if (op_type == MTS_READ) |
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*data = 0xFFFE; |
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break; |
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|
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/* |
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* Network interrupt status. |
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* |
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* Bit 0: 0 = Interrupt for slot 1 |
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* Bit 4: 0 = Interrupt for slot 2 |
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* Bit 8: 0 = Interrupt for slot 3 |
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* Bit 12: 0 = Interrupt for slot 4 |
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*/ |
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case 0x000022: |
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if (op_type == MTS_READ) |
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*data = 0x0000; |
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vm_clear_irq(d->router->vm,C3745_NETIO_IRQ); |
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break; |
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|
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/* |
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* Per Slot Intr Mask (seen with "sh platform"). |
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* IO Mask 1 is the lower 8-bits. |
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*/ |
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case 0x00002a: |
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if (op_type == MTS_READ) |
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*data = d->intr_mask; |
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else |
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d->intr_mask = *data; |
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break; |
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|
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/* IO Mask 2 (seen with "sh platform") */ |
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case 0x00002c: |
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if (op_type == MTS_READ) |
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*data = d->io_mask2; |
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else |
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d->io_mask2 = *data; |
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break; |
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|
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/* EEPROM in slots 1-4 */ |
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case 0x000040: |
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case 0x000042: |
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case 0x000044: |
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case 0x000046: |
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slot = (offset - 0x000040) >> 1; |
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|
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if (op_type == MTS_WRITE) |
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nmc93c46_write(&d->router->nm_eeprom_group[slot],(u_int)(*data)); |
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else |
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*data = nmc93c46_read(&d->router->nm_eeprom_group[slot]); |
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break; |
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|
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/* AIM slot 0 EEPROM */ |
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case 0x000048: |
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if (op_type == MTS_READ) |
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*data = 0xFFFF; |
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break; |
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|
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/* AIM slot 1 EEPROM */ |
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case 0x00004A: |
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if (op_type == MTS_READ) |
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*data = 0xFFFF; |
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break; |
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|
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/* |
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* NM presence. |
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* |
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* Bit 0: 0 = NM present in slot 2 (0x42) |
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* Bit 4: 0 = NM present in slot 4 (0x46) |
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* Bit 8: 0 = NM present in slot 1 (0x40) |
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* Bit 12: 0 = NM present in slot 3 (0x44) |
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*/ |
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case 0x00004e: |
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if (op_type == MTS_READ) { |
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*data = 0xFFFF; |
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|
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if (c3745_nm_check_eeprom(d->router,1)) |
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*data &= ~0x0100; |
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|
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if (c3745_nm_check_eeprom(d->router,2)) |
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*data &= ~0x0001; |
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|
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if (c3745_nm_check_eeprom(d->router,3)) |
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*data &= ~0x1000; |
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|
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if (c3745_nm_check_eeprom(d->router,4)) |
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*data &= ~0x0010; |
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} |
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break; |
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|
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/* VWIC/WIC related */ |
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case 0x100004: |
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case 0x100006: |
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case 0x100008: |
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if (op_type == MTS_READ) |
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*data = 0xFFFF; |
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break; |
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|
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#if DEBUG_UNKNOWN |
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default: |
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if (op_type == MTS_READ) { |
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cpu_log(cpu,"IO_FPGA", |
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"read from unknown addr 0x%x, pc=0x%llx (size=%u)\n", |
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offset,cpu_get_pc(cpu),op_size); |
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} else { |
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cpu_log(cpu,"IO_FPGA", |
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"write to unknown addr 0x%x, value=0x%llx, " |
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"pc=0x%llx (size=%u)\n", |
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offset,*data,cpu_get_pc(cpu),op_size); |
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} |
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#endif |
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} |
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|
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return NULL; |
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} |
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|
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/* Initialize EEPROM groups */ |
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void c3745_init_eeprom_groups(c3745_t *router) |
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{ |
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int i; |
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|
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/* Initialize Mainboard EEPROM */ |
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router->sys_eeprom_group = eeprom_sys_group; |
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|
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for(i=0;i<3;i++) { |
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router->sys_eeprom_group.eeprom[i] = &router->sys_eeprom[i]; |
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router->sys_eeprom[i].data = NULL; |
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router->sys_eeprom[i].len = 0; |
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} |
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|
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/* EEPROMs for Network Modules */ |
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for(i=1;i<=4;i++) { |
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router->nm_eeprom_group[i-1] = eeprom_nm_group; |
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router->nm_eeprom_group[i-1].eeprom[0] = &router->nm_bay[i].eeprom; |
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} |
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} |
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|
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/* Shutdown the IO FPGA device */ |
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void dev_c3745_iofpga_shutdown(vm_instance_t *vm,struct iofpga_data *d) |
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{ |
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if (d != NULL) { |
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/* Remove the device */ |
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dev_remove(vm,&d->dev); |
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|
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/* Free the structure itself */ |
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free(d); |
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} |
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} |
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|
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/* |
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* dev_c3745_iofpga_init() |
| 356 |
*/ |
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int dev_c3745_iofpga_init(c3745_t *router,m_uint64_t paddr,m_uint32_t len) |
| 358 |
{ |
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vm_instance_t *vm = router->vm; |
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struct iofpga_data *d; |
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|
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/* Allocate private data structure */ |
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if (!(d = malloc(sizeof(*d)))) { |
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fprintf(stderr,"IO_FPGA: out of memory\n"); |
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return(-1); |
| 366 |
} |
| 367 |
|
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memset(d,0,sizeof(*d)); |
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d->router = router; |
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|
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vm_object_init(&d->vm_obj); |
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d->vm_obj.name = "io_fpga"; |
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d->vm_obj.data = d; |
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d->vm_obj.shutdown = (vm_shutdown_t)dev_c3745_iofpga_shutdown; |
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|
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/* Set device properties */ |
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dev_init(&d->dev); |
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d->dev.name = "io_fpga"; |
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d->dev.phys_addr = paddr; |
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d->dev.phys_len = len; |
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d->dev.priv_data = d; |
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d->dev.handler = dev_c3745_iofpga_access; |
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|
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/* Map this device to the VM */ |
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vm_bind_device(router->vm,&d->dev); |
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vm_object_add(vm,&d->vm_obj); |
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return(0); |
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} |
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