/[dynamips]/upstream/dynamips-0.2.6-RC3/x86_trans.h
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Annotation of /upstream/dynamips-0.2.6-RC3/x86_trans.h

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Sat Oct 6 16:06:49 2007 UTC (14 years, 10 months ago) by dpavlin
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dynamips-0.2.6-RC3

1 dpavlin 1 /*
2     * Cisco 7200 (Predator) simulation platform.
3     * Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr)
4     */
5    
6     #ifndef __X86_TRANS_H__
7     #define __X86_TRANS_H__
8    
9     #include "utils.h"
10     #include "x86-codegen.h"
11     #include "mips64.h"
12     #include "dynamips.h"
13     #include "cp0.h"
14     #include "mips64_exec.h"
15    
16     #define JIT_SUPPORT 1
17    
18     /* Manipulate bitmasks atomically */
19     static forced_inline void atomic_or(m_uint32_t *v,m_uint32_t m)
20     {
21     __asm__ __volatile__("lock; orl %1,%0":"=m"(*v):"ir"(m),"m"(*v));
22     }
23    
24     static forced_inline void atomic_and(m_uint32_t *v,m_uint32_t m)
25     {
26     __asm__ __volatile__("lock; andl %1,%0":"=m"(*v):"ir"(m),"m"(*v));
27     }
28    
29     /* Wrappers to x86-codegen functions */
30     #define insn_block_set_patch x86_patch
31     #define insn_block_set_jump x86_jump_code
32    
33     /* MIPS instruction array */
34     extern struct insn_tag mips64_insn_tags[];
35    
36     /* Push epilog for an x86 instruction block */
37     static forced_inline void insn_block_push_epilog(insn_block_t *block)
38     {
39     x86_ret(block->jit_ptr);
40     }
41    
42     /* Execute JIT code */
43     static forced_inline
44     void insn_block_exec_jit_code(cpu_mips_t *cpu,insn_block_t *block)
45     {
46     insn_tblock_fptr jit_code;
47     m_uint32_t offset;
48    
49     offset = (cpu->pc & MIPS_MIN_PAGE_IMASK) >> 2;
50     jit_code = (insn_tblock_fptr)block->jit_insn_ptr[offset];
51    
52     if (unlikely(!jit_code)) {
53     mips64_exec_single_step(cpu,vmtoh32(block->mips_code[offset]));
54     return;
55     }
56    
57     asm volatile ("movl %0,%%edi"::"r"(cpu):
58     "esi","edi","eax","ebx","ecx","edx");
59     jit_code();
60     }
61    
62     /* Set the Pointer Counter (PC) register */
63     void mips64_set_pc(insn_block_t *b,m_uint64_t new_pc);
64    
65     /* Set the Return Address (RA) register */
66     void mips64_set_ra(insn_block_t *b,m_uint64_t ret_pc);
67    
68     /* Virtual Breakpoint */
69     void mips64_emit_breakpoint(insn_block_t *b);
70    
71     /* Emit unhandled instruction code */
72     int mips64_emit_invalid_delay_slot(insn_block_t *b);
73    
74     /*
75     * Increment count register and trigger the timer IRQ if value in compare
76     * register is the same.
77     */
78     void mips64_inc_cp0_count_reg(insn_block_t *b);
79    
80     /* Increment the number of executed instructions (performance debugging) */
81     void mips64_inc_perf_counter(insn_block_t *b);
82    
83     #endif

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