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dpavlin |
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/* |
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* Cisco 7200 (Predator) simulation platform. |
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* Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr) |
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* |
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* XXX TODO: proper context save/restore for CPUs. |
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*/ |
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <unistd.h> |
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#include <string.h> |
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#include <sys/types.h> |
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#include <sys/stat.h> |
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#include <sys/mman.h> |
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#include <fcntl.h> |
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#include <assert.h> |
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#include "rbtree.h" |
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#include "mips64.h" |
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#include "dynamips.h" |
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#include "cp0.h" |
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#include "mips64_exec.h" |
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#include "memory.h" |
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#include "device.h" |
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/* MIPS general purpose registers names */ |
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char *mips64_gpr_reg_names[MIPS64_GPR_NR] = { |
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"zr", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
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"t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", |
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"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", |
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"t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra", |
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}; |
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/* Cacheability and Coherency Attribute */ |
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static int cca_cache_status[8] = { |
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1, 1, 0, 1, 0, 1, 0, 0, |
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}; |
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/* Get register index given its name */ |
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int mips64_get_reg_index(char *name) |
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{ |
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int i; |
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for(i=0;i<MIPS64_GPR_NR;i++) |
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if (!strcmp(mips64_gpr_reg_names[i],name)) |
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return(i); |
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return(-1); |
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} |
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/* Get cacheability info */ |
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int mips64_cca_cached(m_uint8_t val) |
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{ |
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return(cca_cache_status[val & 0x03]); |
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} |
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/* Reset a MIPS64 CPU */ |
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int mips64_reset(cpu_mips_t *cpu) |
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{ |
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cpu->pc = MIPS_ROM_PC; |
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cpu->gpr[MIPS_GPR_SP] = MIPS_ROM_SP; |
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cpu->cp0.reg[MIPS_CP0_STATUS] = MIPS_CP0_STATUS_BEV; |
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cpu->cp0.reg[MIPS_CP0_CAUSE] = 0; |
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cpu->cp0.reg[MIPS_CP0_CONFIG] = 0x00c08ff0ULL; |
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/* Clear the complete TLB */ |
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memset(&cpu->cp0.tlb,0,MIPS64_TLB_MAX_ENTRIES*sizeof(tlb_entry_t)); |
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/* Restart the MTS subsystem */ |
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mts_shutdown(cpu); |
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mts64_init(cpu); |
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mts_init_memop_vectors(cpu); |
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cpu->mts_rebuild(cpu); |
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/* Flush JIT structures */ |
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mips64_jit_flush(cpu,0); |
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return(0); |
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} |
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/* Initialize a MIPS64 processor */ |
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int mips64_init(cpu_mips_t *cpu) |
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{ |
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cpu->state = MIPS_CPU_SUSPENDED; |
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cpu->addr_bus_mask = 0xFFFFFFFFFFFFFFFFULL; |
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cpu->cp0.reg[MIPS_CP0_PRID] = MIPS_PRID_R4600; |
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cpu->cp0.tlb_entries = MIPS64_TLB_STD_ENTRIES; |
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/* Initialize idle timer */ |
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cpu->idle_max = 1500; |
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cpu->idle_sleep_time = 50000; |
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/* Timer IRQ parameters (default frequency: 250 Hz <=> 4ms period) */ |
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cpu->timer_irq_check_itv = 1000; |
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cpu->timer_irq_freq = 250; |
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/* Enable fast memory operations */ |
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cpu->fast_memop = TRUE; |
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/* Create the IRQ lock (for non-jit architectures) */ |
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pthread_mutex_init(&cpu->irq_lock,NULL); |
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/* Idle loop mutex and condition */ |
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pthread_mutex_init(&cpu->idle_mutex,NULL); |
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pthread_cond_init(&cpu->idle_cond,NULL); |
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/* Set the startup parameters */ |
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mips64_reset(cpu); |
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return(0); |
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} |
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/* Delete a MIPS64 processor */ |
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void mips64_delete(cpu_mips_t *cpu) |
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{ |
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if (cpu) { |
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mts_shutdown(cpu); |
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mips64_jit_shutdown(cpu); |
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free(cpu); |
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} |
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} |
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/* Set the CPU PRID register */ |
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void mips64_set_prid(cpu_mips_t *cpu,m_uint32_t prid) |
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{ |
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cpu->cp0.reg[MIPS_CP0_PRID] = prid; |
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if ((prid == MIPS_PRID_R7000) || (prid == MIPS_PRID_BCM1250)) |
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cpu->cp0.tlb_entries = MIPS64_TLB_MAX_ENTRIES; |
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} |
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/* Virtual idle loop */ |
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void mips64_idle_loop(cpu_mips_t *cpu) |
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{ |
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struct timespec t_spc; |
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m_tmcnt_t expire; |
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expire = m_gettime_usec() + cpu->idle_sleep_time; |
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pthread_mutex_lock(&cpu->idle_mutex); |
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t_spc.tv_sec = expire / 1000000; |
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t_spc.tv_nsec = (expire % 1000000) * 1000; |
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pthread_cond_timedwait(&cpu->idle_cond,&cpu->idle_mutex,&t_spc); |
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pthread_mutex_unlock(&cpu->idle_mutex); |
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} |
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/* Break idle wait state */ |
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void mips64_idle_break_wait(cpu_mips_t *cpu) |
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{ |
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pthread_cond_signal(&cpu->idle_cond); |
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dpavlin |
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cpu->idle_count = 0; |
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dpavlin |
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} |
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/* Timer IRQ */ |
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void *mips64_timer_irq_run(cpu_mips_t *cpu) |
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{ |
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pthread_mutex_t umutex = PTHREAD_MUTEX_INITIALIZER; |
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pthread_cond_t ucond = PTHREAD_COND_INITIALIZER; |
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struct timespec t_spc; |
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m_tmcnt_t expire; |
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u_int interval; |
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u_int threshold; |
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interval = 1000000 / cpu->timer_irq_freq; |
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threshold = cpu->timer_irq_freq * 10; |
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expire = m_gettime_usec() + interval; |
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while(cpu->state != MIPS_CPU_HALTED) { |
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pthread_mutex_lock(&umutex); |
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t_spc.tv_sec = expire / 1000000; |
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t_spc.tv_nsec = (expire % 1000000) * 1000; |
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pthread_cond_timedwait(&ucond,&umutex,&t_spc); |
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pthread_mutex_unlock(&umutex); |
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if (likely(!cpu->irq_disable) && |
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likely(cpu->state == MIPS_CPU_RUNNING)) |
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{ |
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cpu->timer_irq_pending++; |
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if (unlikely(cpu->timer_irq_pending > threshold)) { |
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cpu->timer_irq_pending = 0; |
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cpu->timer_drift++; |
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#if 0 |
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printf("Timer IRQ not accurate (%u pending IRQ): " |
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"reduce the \"--timer-irq-check-itv\" parameter " |
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"(current value: %u)\n", |
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cpu->timer_irq_pending,cpu->timer_irq_check_itv); |
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#endif |
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} |
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} |
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expire += interval; |
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} |
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return NULL; |
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} |
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dpavlin |
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#define IDLE_HASH_SIZE 8192 |
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dpavlin |
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/* Idle PC hash item */ |
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dpavlin |
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struct mips64_idle_pc_hash { |
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dpavlin |
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m_uint64_t pc; |
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u_int count; |
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dpavlin |
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struct mips64_idle_pc_hash *next; |
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dpavlin |
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}; |
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/* Determine an "idling" PC */ |
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int mips64_get_idling_pc(cpu_mips_t *cpu) |
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{ |
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dpavlin |
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struct mips64_idle_pc_hash **pc_hash,*p; |
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struct mips64_idle_pc *res; |
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dpavlin |
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u_int h_index,res_count; |
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m_uint64_t cur_pc; |
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int i; |
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dpavlin |
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cpu->idle_pc_prop_count = 0; |
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dpavlin |
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if (cpu->idle_pc != 0) { |
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printf("\nYou already use an idle PC, using the calibration would give " |
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"incorrect results.\n"); |
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return(-1); |
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} |
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printf("\nPlease wait while gathering statistics...\n"); |
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pc_hash = calloc(IDLE_HASH_SIZE,sizeof(struct mips64_idle_pc *)); |
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/* Disable IRQ */ |
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cpu->irq_disable = TRUE; |
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/* Take 1000 measures, each mesure every 10ms */ |
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for(i=0;i<1000;i++) { |
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cur_pc = cpu->pc; |
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h_index = (cur_pc >> 2) & (IDLE_HASH_SIZE-1); |
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for(p=pc_hash[h_index];p;p=p->next) |
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if (p->pc == cur_pc) { |
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p->count++; |
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break; |
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} |
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if (!p) { |
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if ((p = malloc(sizeof(*p)))) { |
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p->pc = cur_pc; |
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p->count = 1; |
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p->next = pc_hash[h_index]; |
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pc_hash[h_index] = p; |
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} |
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} |
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usleep(10000); |
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} |
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/* Select PCs */ |
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for(i=0,res_count=0;i<IDLE_HASH_SIZE;i++) { |
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for(p=pc_hash[i];p;p=p->next) |
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if ((p->count >= 20) && (p->count <= 80)) { |
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dpavlin |
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res = &cpu->idle_pc_prop[cpu->idle_pc_prop_count++]; |
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dpavlin |
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dpavlin |
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res->pc = p->pc; |
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res->count = p->count; |
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if (cpu->idle_pc_prop_count >= MIPS64_IDLE_PC_MAX_RES) |
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dpavlin |
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goto done; |
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} |
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} |
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done: |
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/* Set idle PC */ |
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dpavlin |
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if (cpu->idle_pc_prop_count) { |
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dpavlin |
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printf("Done. Suggested idling PC:\n"); |
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dpavlin |
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for(i=0;i<cpu->idle_pc_prop_count;i++) { |
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printf(" 0x%llx (count=%u)\n", |
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cpu->idle_pc_prop[i].pc, |
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cpu->idle_pc_prop[i].count); |
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} |
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dpavlin |
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printf("Restart the emulator with \"--idle-pc=0x%llx\" (for example)\n", |
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dpavlin |
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cpu->idle_pc_prop[0].pc); |
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dpavlin |
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} else { |
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printf("Done. No suggestion for idling PC\n"); |
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} |
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/* Re-enable IRQ */ |
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cpu->irq_disable = FALSE; |
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return(0); |
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} |
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/* Update the IRQ flag (inline) */ |
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static forced_inline int mips64_update_irq_flag_fast(cpu_mips_t *cpu) |
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{ |
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mips_cp0_t *cp0 = &cpu->cp0; |
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m_uint32_t imask,sreg_mask; |
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m_uint32_t cause; |
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cpu->irq_pending = FALSE; |
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cause = cp0->reg[MIPS_CP0_CAUSE] & ~MIPS_CP0_CAUSE_IMASK; |
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cp0->reg[MIPS_CP0_CAUSE] = cause | cpu->irq_cause; |
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sreg_mask = MIPS_CP0_STATUS_IE|MIPS_CP0_STATUS_EXL|MIPS_CP0_STATUS_ERL; |
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if ((cp0->reg[MIPS_CP0_STATUS] & sreg_mask) == MIPS_CP0_STATUS_IE) { |
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imask = cp0->reg[MIPS_CP0_STATUS] & MIPS_CP0_STATUS_IMASK; |
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if (unlikely(cp0->reg[MIPS_CP0_CAUSE] & imask)) { |
305 |
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cpu->irq_pending = TRUE; |
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return(TRUE); |
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} |
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} |
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return(FALSE); |
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} |
312 |
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313 |
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/* Update the IRQ flag */ |
314 |
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void mips64_update_irq_flag(cpu_mips_t *cpu) |
315 |
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{ |
316 |
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mips64_update_irq_flag_fast(cpu); |
317 |
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} |
318 |
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319 |
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/* Generate an exception */ |
320 |
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void mips64_trigger_exception(cpu_mips_t *cpu,u_int exc_code,int bd_slot) |
321 |
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{ |
322 |
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mips_cp0_t *cp0 = &cpu->cp0; |
323 |
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m_uint64_t cause,vector; |
324 |
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325 |
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/* we don't set EPC if EXL is set */ |
326 |
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if (!(cp0->reg[MIPS_CP0_STATUS] & MIPS_CP0_STATUS_EXL)) |
327 |
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{ |
328 |
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cp0->reg[MIPS_CP0_EPC] = cpu->pc; |
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330 |
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/* keep IM, set exception code and bd slot */ |
331 |
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cause = cp0->reg[MIPS_CP0_CAUSE] & MIPS_CP0_CAUSE_IMASK; |
332 |
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333 |
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if (bd_slot) |
334 |
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cause |= MIPS_CP0_CAUSE_BD_SLOT; |
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else |
336 |
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cause &= ~MIPS_CP0_CAUSE_BD_SLOT; |
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338 |
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cause |= (exc_code << MIPS_CP0_CAUSE_SHIFT); |
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cp0->reg[MIPS_CP0_CAUSE] = cause; |
340 |
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341 |
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/* XXX properly set vector */ |
342 |
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vector = 0x180ULL; |
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} |
344 |
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else |
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{ |
346 |
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/* keep IM and set exception code */ |
347 |
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cause = cp0->reg[MIPS_CP0_CAUSE] & MIPS_CP0_CAUSE_IMASK; |
348 |
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cause |= (exc_code << MIPS_CP0_CAUSE_SHIFT); |
349 |
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cp0->reg[MIPS_CP0_CAUSE] = cause; |
350 |
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351 |
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/* set vector */ |
352 |
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vector = 0x180ULL; |
353 |
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} |
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355 |
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/* Set EXL bit in status register */ |
356 |
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cp0->reg[MIPS_CP0_STATUS] |= MIPS_CP0_STATUS_EXL; |
357 |
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358 |
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/* Use bootstrap vectors ? */ |
359 |
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if (cp0->reg[MIPS_CP0_STATUS] & MIPS_CP0_STATUS_BEV) |
360 |
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cpu->pc = 0xffffffffbfc00200ULL + vector; |
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else |
362 |
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cpu->pc = 0xffffffff80000000ULL + vector; |
363 |
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364 |
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/* Clear the pending IRQ flag */ |
365 |
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cpu->irq_pending = 0; |
366 |
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} |
367 |
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368 |
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/* |
369 |
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* Increment count register and trigger the timer IRQ if value in compare |
370 |
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* register is the same. |
371 |
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*/ |
372 |
|
|
fastcall void mips64_exec_inc_cp0_cnt(cpu_mips_t *cpu) |
373 |
|
|
{ |
374 |
|
|
cpu->cp0_virt_cnt_reg++; |
375 |
|
|
|
376 |
|
|
#if 0 /* TIMER_IRQ */ |
377 |
|
|
mips_cp0_t *cp0 = &cpu->cp0; |
378 |
|
|
|
379 |
|
|
if (unlikely((cpu->cp0_virt_cnt_reg == cpu->cp0_virt_cmp_reg))) { |
380 |
|
|
cp0->reg[MIPS_CP0_COUNT] = (m_uint32_t)cp0->reg[MIPS_CP0_COMPARE]; |
381 |
|
|
mips64_set_irq(cpu,7); |
382 |
|
|
mips64_update_irq_flag_fast(cpu); |
383 |
|
|
} |
384 |
|
|
#endif |
385 |
|
|
} |
386 |
|
|
|
387 |
|
|
/* Trigger the Timer IRQ */ |
388 |
|
|
fastcall void mips64_trigger_timer_irq(cpu_mips_t *cpu) |
389 |
|
|
{ |
390 |
|
|
mips_cp0_t *cp0 = &cpu->cp0; |
391 |
|
|
|
392 |
|
|
cpu->timer_irq_count++; |
393 |
|
|
|
394 |
|
|
cp0->reg[MIPS_CP0_COUNT] = (m_uint32_t)cp0->reg[MIPS_CP0_COMPARE]; |
395 |
|
|
mips64_set_irq(cpu,7); |
396 |
|
|
mips64_update_irq_flag_fast(cpu); |
397 |
|
|
} |
398 |
|
|
|
399 |
|
|
/* Execute ERET instruction */ |
400 |
|
|
fastcall void mips64_exec_eret(cpu_mips_t *cpu) |
401 |
|
|
{ |
402 |
|
|
mips_cp0_t *cp0 = &cpu->cp0; |
403 |
|
|
|
404 |
|
|
if (cp0->reg[MIPS_CP0_STATUS] & MIPS_CP0_STATUS_ERL) { |
405 |
|
|
cp0->reg[MIPS_CP0_STATUS] &= ~MIPS_CP0_STATUS_ERL; |
406 |
|
|
cpu->pc = cp0->reg[MIPS_CP0_ERR_EPC]; |
407 |
|
|
} else { |
408 |
|
|
cp0->reg[MIPS_CP0_STATUS] &= ~MIPS_CP0_STATUS_EXL; |
409 |
|
|
cpu->pc = cp0->reg[MIPS_CP0_EPC]; |
410 |
|
|
} |
411 |
|
|
|
412 |
|
|
/* We have to clear the LLbit */ |
413 |
|
|
cpu->ll_bit = 0; |
414 |
|
|
|
415 |
|
|
/* Update the pending IRQ flag */ |
416 |
|
|
mips64_update_irq_flag_fast(cpu); |
417 |
|
|
} |
418 |
|
|
|
419 |
|
|
/* Execute SYSCALL instruction */ |
420 |
|
|
fastcall void mips64_exec_syscall(cpu_mips_t *cpu) |
421 |
|
|
{ |
422 |
|
|
#if DEBUG_SYSCALL |
423 |
|
|
printf("MIPS64: SYSCALL at PC=0x%llx (RA=0x%llx)\n" |
424 |
|
|
" a0=0x%llx, a1=0x%llx, a2=0x%llx, a3=0x%llx\n", |
425 |
|
|
cpu->pc, cpu->gpr[MIPS_GPR_RA], |
426 |
|
|
cpu->gpr[MIPS_GPR_A0], cpu->gpr[MIPS_GPR_A1], |
427 |
|
|
cpu->gpr[MIPS_GPR_A2], cpu->gpr[MIPS_GPR_A3]); |
428 |
|
|
#endif |
429 |
|
|
|
430 |
|
|
/* XXX TODO: Branch Delay slot */ |
431 |
|
|
mips64_trigger_exception(cpu,MIPS_CP0_CAUSE_SYSCALL,0); |
432 |
|
|
} |
433 |
|
|
|
434 |
|
|
/* Execute BREAK instruction */ |
435 |
|
|
fastcall void mips64_exec_break(cpu_mips_t *cpu,u_int code) |
436 |
|
|
{ |
437 |
|
|
printf("MIPS64: BREAK instruction (code=%u)\n",code); |
438 |
|
|
mips64_dump_regs(cpu); |
439 |
|
|
|
440 |
|
|
/* XXX TODO: Branch Delay slot */ |
441 |
|
|
mips64_trigger_exception(cpu,MIPS_CP0_CAUSE_BP,0); |
442 |
|
|
} |
443 |
|
|
|
444 |
|
|
/* Trigger a Trap Exception */ |
445 |
|
|
fastcall void mips64_trigger_trap_exception(cpu_mips_t *cpu) |
446 |
|
|
{ |
447 |
|
|
/* XXX TODO: Branch Delay slot */ |
448 |
|
|
printf("MIPS64: TRAP exception, CPU=%p\n",cpu); |
449 |
|
|
mips64_trigger_exception(cpu,MIPS_CP0_CAUSE_TRAP,0); |
450 |
|
|
} |
451 |
|
|
|
452 |
|
|
/* Trigger IRQs */ |
453 |
|
|
fastcall void mips64_trigger_irq(cpu_mips_t *cpu) |
454 |
|
|
{ |
455 |
|
|
if (unlikely(cpu->irq_disable)) { |
456 |
|
|
cpu->irq_pending = 0; |
457 |
|
|
return; |
458 |
|
|
} |
459 |
|
|
|
460 |
|
|
cpu->irq_count++; |
461 |
|
|
if (mips64_update_irq_flag_fast(cpu)) |
462 |
|
|
mips64_trigger_exception(cpu,MIPS_CP0_CAUSE_INTERRUPT,0); |
463 |
|
|
else |
464 |
|
|
cpu->irq_fp_count++; |
465 |
|
|
} |
466 |
|
|
|
467 |
|
|
/* DMFC1 */ |
468 |
|
|
fastcall void mips64_exec_dmfc1(cpu_mips_t *cpu,u_int gp_reg,u_int cp1_reg) |
469 |
|
|
{ |
470 |
|
|
cpu->gpr[gp_reg] = cpu->fpu.reg[cp1_reg]; |
471 |
|
|
} |
472 |
|
|
|
473 |
|
|
/* DMTC1 */ |
474 |
|
|
fastcall void mips64_exec_dmtc1(cpu_mips_t *cpu,u_int gp_reg,u_int cp1_reg) |
475 |
|
|
{ |
476 |
|
|
cpu->fpu.reg[cp1_reg] = cpu->gpr[gp_reg]; |
477 |
|
|
} |
478 |
|
|
|
479 |
|
|
/* MFC1 */ |
480 |
|
|
fastcall void mips64_exec_mfc1(cpu_mips_t *cpu,u_int gp_reg,u_int cp1_reg) |
481 |
|
|
{ |
482 |
|
|
m_int64_t val; |
483 |
|
|
|
484 |
|
|
val = cpu->fpu.reg[cp1_reg] & 0xffffffff; |
485 |
|
|
cpu->gpr[gp_reg] = sign_extend(val,32); |
486 |
|
|
} |
487 |
|
|
|
488 |
|
|
/* MTC1 */ |
489 |
|
|
fastcall void mips64_exec_mtc1(cpu_mips_t *cpu,u_int gp_reg,u_int cp1_reg) |
490 |
|
|
{ |
491 |
|
|
cpu->fpu.reg[cp1_reg] = cpu->gpr[gp_reg] & 0xffffffff; |
492 |
|
|
} |
493 |
|
|
|
494 |
|
|
/* Virtual breakpoint */ |
495 |
|
|
fastcall void mips64_run_breakpoint(cpu_mips_t *cpu) |
496 |
|
|
{ |
497 |
|
|
cpu_log(cpu,"BREAKPOINT", |
498 |
|
|
"Virtual breakpoint reached at PC=0x%llx\n",cpu->pc); |
499 |
|
|
|
500 |
dpavlin |
2 |
printf("[[[ Virtual Breakpoint reached at PC=0x%llx RA=0x%llx]]]\n", |
501 |
|
|
cpu->pc,cpu->gpr[MIPS_GPR_RA]); |
502 |
|
|
|
503 |
dpavlin |
1 |
mips64_dump_regs(cpu); |
504 |
|
|
memlog_dump(cpu); |
505 |
|
|
} |
506 |
|
|
|
507 |
dpavlin |
2 |
/* Add a virtual breakpoint */ |
508 |
|
|
int mips64_add_breakpoint(cpu_mips_t *cpu,m_uint64_t pc) |
509 |
|
|
{ |
510 |
|
|
int i; |
511 |
|
|
|
512 |
|
|
for(i=0;i<MIPS64_MAX_BREAKPOINTS;i++) |
513 |
|
|
if (!cpu->breakpoints[i]) |
514 |
|
|
break; |
515 |
|
|
|
516 |
|
|
if (i == MIPS64_MAX_BREAKPOINTS) |
517 |
|
|
return(-1); |
518 |
|
|
|
519 |
|
|
cpu->breakpoints[i] = pc; |
520 |
|
|
cpu->breakpoints_enabled = TRUE; |
521 |
|
|
return(0); |
522 |
|
|
} |
523 |
|
|
|
524 |
|
|
/* Remove a virtual breakpoint */ |
525 |
|
|
void mips64_remove_breakpoint(cpu_mips_t *cpu,m_uint64_t pc) |
526 |
|
|
{ |
527 |
|
|
int i,j; |
528 |
|
|
|
529 |
|
|
for(i=0;i<MIPS64_MAX_BREAKPOINTS;i++) |
530 |
|
|
if (cpu->breakpoints[i] == pc) |
531 |
|
|
{ |
532 |
|
|
for(j=i;j<MIPS64_MAX_BREAKPOINTS-1;j++) |
533 |
|
|
cpu->breakpoints[j] = cpu->breakpoints[j+1]; |
534 |
|
|
|
535 |
|
|
cpu->breakpoints[MIPS64_MAX_BREAKPOINTS-1] = 0; |
536 |
|
|
} |
537 |
|
|
|
538 |
|
|
for(i=0;i<MIPS64_MAX_BREAKPOINTS;i++) |
539 |
|
|
if (cpu->breakpoints[i] != 0) |
540 |
|
|
return; |
541 |
|
|
|
542 |
|
|
cpu->breakpoints_enabled = TRUE; |
543 |
|
|
} |
544 |
|
|
|
545 |
dpavlin |
1 |
/* Debugging for register-jump to address 0 */ |
546 |
|
|
fastcall void mips64_debug_jr0(cpu_mips_t *cpu) |
547 |
|
|
{ |
548 |
|
|
printf("MIPS64: cpu %p jumping to address 0...\n",cpu); |
549 |
|
|
mips64_dump_regs(cpu); |
550 |
|
|
} |
551 |
|
|
|
552 |
|
|
/* Dump registers of a MIPS64 processor */ |
553 |
|
|
void mips64_dump_regs(cpu_mips_t *cpu) |
554 |
|
|
{ |
555 |
|
|
mips_insn_t *ptr,insn; |
556 |
|
|
char buffer[80]; |
557 |
|
|
int i; |
558 |
|
|
|
559 |
|
|
printf("MIPS64 Registers:\n"); |
560 |
|
|
|
561 |
|
|
for(i=0;i<MIPS64_GPR_NR/2;i++) { |
562 |
|
|
printf(" %s ($%2d) = 0x%16.16llx %s ($%2d) = 0x%16.16llx\n", |
563 |
|
|
mips64_gpr_reg_names[i*2], i*2, cpu->gpr[i*2], |
564 |
|
|
mips64_gpr_reg_names[(i*2)+1], (i*2)+1, cpu->gpr[(i*2)+1]); |
565 |
|
|
} |
566 |
|
|
|
567 |
|
|
printf(" lo = 0x%16.16llx, hi = 0x%16.16llx\n", cpu->lo, cpu->hi); |
568 |
|
|
printf(" pc = 0x%16.16llx, ll_bit = %u\n", cpu->pc, cpu->ll_bit); |
569 |
|
|
|
570 |
|
|
/* Fetch the current instruction */ |
571 |
|
|
ptr = cpu->mem_op_lookup(cpu,cpu->pc); |
572 |
|
|
if (ptr) { |
573 |
|
|
insn = vmtoh32(*ptr); |
574 |
|
|
|
575 |
|
|
if (mips64_dump_insn(buffer,sizeof(buffer),1,cpu->pc,insn) != -1) |
576 |
|
|
printf(" Instruction: %s\n",buffer); |
577 |
|
|
} |
578 |
|
|
|
579 |
|
|
printf("\nCP0 Registers:\n"); |
580 |
|
|
|
581 |
|
|
for(i=0;i<MIPS64_CP0_REG_NR/2;i++) { |
582 |
|
|
printf(" %-10s ($%2d) = 0x%16.16llx %-10s ($%2d) = 0x%16.16llx\n", |
583 |
|
|
mips64_cp0_reg_names[i*2], i*2, cp0_get_reg(cpu,i*2), |
584 |
|
|
mips64_cp0_reg_names[(i*2)+1], (i*2)+1, cp0_get_reg(cpu,(i*2)+1)); |
585 |
|
|
} |
586 |
|
|
|
587 |
|
|
printf("\n IRQ count: %llu, IRQ false positives: %llu, " |
588 |
|
|
"IRQ Pending: %u\n", |
589 |
|
|
cpu->irq_count,cpu->irq_fp_count,cpu->irq_pending); |
590 |
|
|
|
591 |
|
|
printf(" Timer IRQ count: %llu, pending: %u, timer drift: %u\n\n", |
592 |
|
|
cpu->timer_irq_count,cpu->timer_irq_pending,cpu->timer_drift); |
593 |
|
|
|
594 |
|
|
printf("\n"); |
595 |
|
|
} |
596 |
|
|
|
597 |
|
|
/* Dump a memory block */ |
598 |
|
|
void mips64_dump_memory(cpu_mips_t *cpu,m_uint64_t vaddr,u_int count) |
599 |
|
|
{ |
600 |
|
|
void *haddr; |
601 |
|
|
u_int i; |
602 |
|
|
|
603 |
|
|
for(i=0;i<count;i++,vaddr+=4) |
604 |
|
|
{ |
605 |
|
|
if ((i & 3) == 0) |
606 |
|
|
printf("\n 0x%16.16llx: ",vaddr); |
607 |
|
|
|
608 |
|
|
haddr = cpu->mem_op_lookup(cpu,vaddr); |
609 |
|
|
|
610 |
|
|
if (haddr) |
611 |
|
|
printf("0x%8.8x ",htovm32(*(m_uint32_t *)haddr)); |
612 |
|
|
else |
613 |
|
|
printf("XXXXXXXXXX "); |
614 |
|
|
} |
615 |
|
|
|
616 |
|
|
printf("\n\n"); |
617 |
|
|
} |
618 |
|
|
|
619 |
|
|
/* Dump the stack */ |
620 |
|
|
void mips64_dump_stack(cpu_mips_t *cpu,u_int count) |
621 |
|
|
{ |
622 |
|
|
printf("MIPS Stack Dump at 0x%16.16llx:",cpu->gpr[MIPS_GPR_SP]); |
623 |
|
|
mips64_dump_memory(cpu,cpu->gpr[MIPS_GPR_SP],count); |
624 |
|
|
} |
625 |
|
|
|
626 |
|
|
/* Save the CPU state into a file */ |
627 |
|
|
int mips64_save_state(cpu_mips_t *cpu,char *filename) |
628 |
|
|
{ |
629 |
|
|
FILE *fd; |
630 |
|
|
int i; |
631 |
|
|
|
632 |
|
|
if (!(fd = fopen(filename,"w"))) { |
633 |
|
|
perror("mips64_save_state: fopen"); |
634 |
|
|
return(-1); |
635 |
|
|
} |
636 |
|
|
|
637 |
|
|
/* pc, lo and hi */ |
638 |
|
|
fprintf(fd,"pc: %16.16llx\n",cpu->pc); |
639 |
|
|
fprintf(fd,"lo: %16.16llx\n",cpu->lo); |
640 |
|
|
fprintf(fd,"hi: %16.16llx\n",cpu->hi); |
641 |
|
|
|
642 |
|
|
/* general purpose registers */ |
643 |
|
|
for(i=0;i<MIPS64_GPR_NR;i++) |
644 |
|
|
fprintf(fd,"%s: %16.16llx\n", |
645 |
|
|
mips64_gpr_reg_names[i],cpu->gpr[i]); |
646 |
|
|
|
647 |
|
|
printf("\n"); |
648 |
|
|
|
649 |
|
|
/* cp0 registers */ |
650 |
|
|
for(i=0;i<MIPS64_CP0_REG_NR;i++) |
651 |
|
|
fprintf(fd,"%s: %16.16llx\n", |
652 |
|
|
mips64_cp0_reg_names[i],cpu->cp0.reg[i]); |
653 |
|
|
|
654 |
|
|
printf("\n"); |
655 |
|
|
|
656 |
|
|
/* cp1 registers */ |
657 |
|
|
for(i=0;i<MIPS64_CP1_REG_NR;i++) |
658 |
|
|
fprintf(fd,"fpu%d: %16.16llx\n",i,cpu->fpu.reg[i]); |
659 |
|
|
|
660 |
|
|
printf("\n"); |
661 |
|
|
|
662 |
|
|
/* tlb entries */ |
663 |
|
|
for(i=0;i<cpu->cp0.tlb_entries;i++) { |
664 |
|
|
fprintf(fd,"tlb%d_mask: %16.16llx\n",i,cpu->cp0.tlb[i].mask); |
665 |
|
|
fprintf(fd,"tlb%d_hi: %16.16llx\n",i,cpu->cp0.tlb[i].hi); |
666 |
|
|
fprintf(fd,"tlb%d_lo0: %16.16llx\n",i,cpu->cp0.tlb[i].lo0); |
667 |
|
|
fprintf(fd,"tlb%d_lo1: %16.16llx\n",i,cpu->cp0.tlb[i].lo1); |
668 |
|
|
} |
669 |
|
|
|
670 |
|
|
fclose(fd); |
671 |
|
|
return(0); |
672 |
|
|
} |
673 |
|
|
|
674 |
|
|
/* Read a 64-bit unsigned integer */ |
675 |
|
|
static m_uint64_t mips64_hex_u64(char *str,int *err) |
676 |
|
|
{ |
677 |
|
|
m_uint64_t res = 0; |
678 |
|
|
u_char c; |
679 |
|
|
|
680 |
|
|
/* remove leading spaces */ |
681 |
|
|
while((*str == ' ') || (*str == '\t')) |
682 |
|
|
str++; |
683 |
|
|
|
684 |
|
|
while(*str) { |
685 |
|
|
c = *str; |
686 |
|
|
|
687 |
|
|
if ((c >= '0') && (c <= '9')) |
688 |
|
|
res = (res << 4) + (c - '0'); |
689 |
|
|
|
690 |
|
|
if ((c >= 'a') && (c <= 'f')) |
691 |
|
|
res = (res << 4) + ((c - 'a') + 10); |
692 |
|
|
|
693 |
|
|
if ((c >= 'A') && (c <= 'F')) |
694 |
|
|
res = (res << 4) + ((c - 'A') + 10); |
695 |
|
|
|
696 |
|
|
str++; |
697 |
|
|
} |
698 |
|
|
|
699 |
|
|
return(res); |
700 |
|
|
} |
701 |
|
|
|
702 |
|
|
/* Restore the CPU state from a file */ |
703 |
|
|
int mips64_restore_state(cpu_mips_t *cpu,char *filename) |
704 |
|
|
{ |
705 |
|
|
char buffer[4096],*sep,*value,*ep,*field; |
706 |
|
|
size_t len; |
707 |
|
|
FILE *fd; |
708 |
|
|
int index; |
709 |
|
|
|
710 |
|
|
if (!(fd = fopen(filename,"r"))) { |
711 |
|
|
perror("mips64_restore_state: fopen"); |
712 |
|
|
return(-1); |
713 |
|
|
} |
714 |
|
|
|
715 |
|
|
while(!feof(fd)) |
716 |
|
|
{ |
717 |
|
|
*buffer = 0; |
718 |
|
|
fgets(buffer,sizeof(buffer),fd); |
719 |
|
|
len = strlen(buffer); |
720 |
|
|
|
721 |
|
|
if (buffer[len-1] == '\n') |
722 |
|
|
buffer[len-1] = 0; |
723 |
|
|
|
724 |
|
|
sep = strchr(buffer,':'); |
725 |
|
|
if (!sep) continue; |
726 |
|
|
|
727 |
|
|
value = sep + 1; |
728 |
|
|
*sep = 0; |
729 |
|
|
|
730 |
|
|
/* gpr ? */ |
731 |
|
|
if ((index = mips64_get_reg_index(buffer)) != -1) { |
732 |
|
|
cpu->gpr[index] = mips64_hex_u64(value,NULL); |
733 |
|
|
continue; |
734 |
|
|
} |
735 |
|
|
|
736 |
|
|
/* cp0 register ? */ |
737 |
|
|
if ((index = cp0_get_reg_index(buffer)) != -1) { |
738 |
|
|
cpu->cp0.reg[index] = mips64_hex_u64(value,NULL); |
739 |
|
|
continue; |
740 |
|
|
} |
741 |
|
|
|
742 |
|
|
/* cp1 register ? */ |
743 |
|
|
if ((len > 3) && (!strncmp(buffer,"fpu",3))) { |
744 |
|
|
index = atoi(buffer+3); |
745 |
|
|
cpu->fpu.reg[index] = mips64_hex_u64(value,NULL); |
746 |
|
|
} |
747 |
|
|
|
748 |
|
|
/* tlb entry ? */ |
749 |
|
|
if ((len > 3) && (!strncmp(buffer,"tlb",3))) { |
750 |
|
|
ep = strchr(buffer,'_'); |
751 |
|
|
|
752 |
|
|
if (ep) { |
753 |
|
|
index = atoi(buffer+3); |
754 |
|
|
field = ep + 1; |
755 |
|
|
|
756 |
|
|
if (!strcmp(field,"mask")) { |
757 |
|
|
cpu->cp0.tlb[index].mask = mips64_hex_u64(value,NULL); |
758 |
|
|
continue; |
759 |
|
|
} |
760 |
|
|
|
761 |
|
|
if (!strcmp(field,"hi")) { |
762 |
|
|
cpu->cp0.tlb[index].hi = mips64_hex_u64(value,NULL); |
763 |
|
|
continue; |
764 |
|
|
} |
765 |
|
|
|
766 |
|
|
if (!strcmp(field,"lo0")) { |
767 |
|
|
cpu->cp0.tlb[index].lo0 = mips64_hex_u64(value,NULL); |
768 |
|
|
continue; |
769 |
|
|
} |
770 |
|
|
|
771 |
|
|
if (!strcmp(field,"lo1")) { |
772 |
|
|
cpu->cp0.tlb[index].lo1 = mips64_hex_u64(value,NULL); |
773 |
|
|
continue; |
774 |
|
|
} |
775 |
|
|
} |
776 |
|
|
} |
777 |
|
|
|
778 |
|
|
/* pc, lo, hi ? */ |
779 |
|
|
if (!strcmp(buffer,"pc")) { |
780 |
|
|
cpu->pc = mips64_hex_u64(value,NULL); |
781 |
|
|
continue; |
782 |
|
|
} |
783 |
|
|
|
784 |
|
|
if (!strcmp(buffer,"lo")) { |
785 |
|
|
cpu->lo = mips64_hex_u64(value,NULL); |
786 |
|
|
continue; |
787 |
|
|
} |
788 |
|
|
|
789 |
|
|
if (!strcmp(buffer,"hi")) { |
790 |
|
|
cpu->hi = mips64_hex_u64(value,NULL); |
791 |
|
|
continue; |
792 |
|
|
} |
793 |
|
|
} |
794 |
|
|
|
795 |
|
|
cp0_map_all_tlb_to_mts(cpu); |
796 |
|
|
|
797 |
|
|
mips64_dump_regs(cpu); |
798 |
|
|
tlb_dump(cpu); |
799 |
|
|
|
800 |
|
|
fclose(fd); |
801 |
|
|
return(0); |
802 |
|
|
} |
803 |
|
|
|
804 |
|
|
/* Load a raw image into the simulated memory */ |
805 |
|
|
int mips64_load_raw_image(cpu_mips_t *cpu,char *filename,m_uint64_t vaddr) |
806 |
|
|
{ |
807 |
|
|
struct stat file_info; |
808 |
|
|
size_t len,clen; |
809 |
|
|
void *haddr; |
810 |
|
|
FILE *bfd; |
811 |
|
|
|
812 |
|
|
if (!(bfd = fopen(filename,"r"))) { |
813 |
|
|
perror("fopen"); |
814 |
|
|
return(-1); |
815 |
|
|
} |
816 |
|
|
|
817 |
|
|
if (fstat(fileno(bfd),&file_info) == -1) { |
818 |
|
|
perror("stat"); |
819 |
|
|
return(-1); |
820 |
|
|
} |
821 |
|
|
|
822 |
|
|
len = file_info.st_size; |
823 |
|
|
|
824 |
|
|
printf("Loading RAW file '%s' at virtual address 0x%llx (size=%lu)\n", |
825 |
|
|
filename,vaddr,(u_long)len); |
826 |
|
|
|
827 |
|
|
while(len > 0) |
828 |
|
|
{ |
829 |
|
|
haddr = cpu->mem_op_lookup(cpu,vaddr); |
830 |
|
|
|
831 |
|
|
if (!haddr) { |
832 |
|
|
fprintf(stderr,"load_raw_image: invalid load address 0x%llx\n", |
833 |
|
|
vaddr); |
834 |
|
|
return(-1); |
835 |
|
|
} |
836 |
|
|
|
837 |
|
|
if (len > MIPS_MIN_PAGE_SIZE) |
838 |
|
|
clen = MIPS_MIN_PAGE_SIZE; |
839 |
|
|
else |
840 |
|
|
clen = len; |
841 |
|
|
|
842 |
|
|
if (fread((u_char *)haddr,clen,1,bfd) != 1) |
843 |
|
|
break; |
844 |
|
|
|
845 |
|
|
vaddr += MIPS_MIN_PAGE_SIZE; |
846 |
|
|
len -= clen; |
847 |
|
|
} |
848 |
|
|
|
849 |
|
|
fclose(bfd); |
850 |
|
|
return(0); |
851 |
|
|
} |
852 |
|
|
|
853 |
|
|
/* Load an ELF image into the simulated memory */ |
854 |
|
|
int mips64_load_elf_image(cpu_mips_t *cpu,char *filename, |
855 |
|
|
m_uint32_t *entry_point) |
856 |
|
|
{ |
857 |
|
|
m_uint64_t vaddr; |
858 |
|
|
void *haddr; |
859 |
|
|
Elf32_Ehdr *ehdr; |
860 |
|
|
Elf32_Shdr *shdr; |
861 |
|
|
Elf_Scn *scn; |
862 |
|
|
Elf *img_elf; |
863 |
|
|
size_t len,clen; |
864 |
|
|
char *name; |
865 |
|
|
int i,fd; |
866 |
|
|
FILE *bfd; |
867 |
|
|
|
868 |
|
|
if (!filename) |
869 |
|
|
return(-1); |
870 |
|
|
|
871 |
|
|
#ifdef __CYGWIN__ |
872 |
|
|
fd = open(filename,O_RDONLY|O_BINARY); |
873 |
|
|
#else |
874 |
|
|
fd = open(filename,O_RDONLY); |
875 |
|
|
#endif |
876 |
|
|
|
877 |
|
|
if (fd == -1) { |
878 |
|
|
perror("load_elf_image: open"); |
879 |
|
|
return(-1); |
880 |
|
|
} |
881 |
|
|
|
882 |
|
|
if (elf_version(EV_CURRENT) == EV_NONE) { |
883 |
|
|
fprintf(stderr,"load_elf_image: library out of date\n"); |
884 |
|
|
return(-1); |
885 |
|
|
} |
886 |
|
|
|
887 |
|
|
if (!(img_elf = elf_begin(fd,ELF_C_READ,NULL))) { |
888 |
|
|
fprintf(stderr,"load_elf_image: elf_begin: %s\n", |
889 |
|
|
elf_errmsg(elf_errno())); |
890 |
|
|
return(-1); |
891 |
|
|
} |
892 |
|
|
|
893 |
|
|
if (!(ehdr = elf32_getehdr(img_elf))) { |
894 |
|
|
fprintf(stderr,"load_elf_image: invalid ELF file\n"); |
895 |
|
|
return(-1); |
896 |
|
|
} |
897 |
|
|
|
898 |
|
|
printf("Loading ELF file '%s'...\n",filename); |
899 |
|
|
bfd = fdopen(fd,"rb"); |
900 |
|
|
|
901 |
|
|
if (!bfd) { |
902 |
|
|
perror("load_elf_image: fdopen"); |
903 |
|
|
return(-1); |
904 |
|
|
} |
905 |
|
|
|
906 |
|
|
for(i=0;i<ehdr->e_shnum;i++) { |
907 |
|
|
scn = elf_getscn(img_elf,i); |
908 |
|
|
|
909 |
|
|
shdr = elf32_getshdr(scn); |
910 |
|
|
name = elf_strptr(img_elf, ehdr->e_shstrndx, (size_t)shdr->sh_name); |
911 |
|
|
len = shdr->sh_size; |
912 |
|
|
|
913 |
|
|
if (!(shdr->sh_flags & SHF_ALLOC) || !len) |
914 |
|
|
continue; |
915 |
|
|
|
916 |
|
|
fseek(bfd,shdr->sh_offset,SEEK_SET); |
917 |
|
|
vaddr = sign_extend(shdr->sh_addr,32); |
918 |
|
|
|
919 |
|
|
if (cpu->vm->debug_level > 0) { |
920 |
|
|
printf(" * Adding section at virtual address 0x%8.8llx " |
921 |
|
|
"(len=0x%8.8lx)\n",vaddr & 0xFFFFFFFF,(u_long)len); |
922 |
|
|
} |
923 |
|
|
|
924 |
|
|
while(len > 0) |
925 |
|
|
{ |
926 |
|
|
haddr = cpu->mem_op_lookup(cpu,vaddr); |
927 |
|
|
|
928 |
|
|
if (!haddr) { |
929 |
|
|
fprintf(stderr,"load_elf_image: invalid load address 0x%llx\n", |
930 |
|
|
vaddr); |
931 |
|
|
return(-1); |
932 |
|
|
} |
933 |
|
|
|
934 |
|
|
if (len > MIPS_MIN_PAGE_SIZE) |
935 |
|
|
clen = MIPS_MIN_PAGE_SIZE; |
936 |
|
|
else |
937 |
|
|
clen = len; |
938 |
|
|
|
939 |
|
|
clen = fread((u_char *)haddr,clen,1,bfd); |
940 |
|
|
|
941 |
|
|
if (clen != 1) |
942 |
|
|
break; |
943 |
|
|
|
944 |
|
|
vaddr += MIPS_MIN_PAGE_SIZE; |
945 |
|
|
len -= clen; |
946 |
|
|
} |
947 |
|
|
} |
948 |
|
|
|
949 |
|
|
printf("ELF entry point: 0x%x\n",ehdr->e_entry); |
950 |
|
|
|
951 |
|
|
if (entry_point) |
952 |
|
|
*entry_point = ehdr->e_entry; |
953 |
|
|
|
954 |
|
|
elf_end(img_elf); |
955 |
|
|
fclose(bfd); |
956 |
|
|
return(0); |
957 |
|
|
} |
958 |
|
|
|
959 |
|
|
/* Symbol lookup */ |
960 |
|
|
struct symbol *mips64_sym_lookup(cpu_mips_t *cpu,m_uint64_t addr) |
961 |
|
|
{ |
962 |
|
|
return(rbtree_lookup(cpu->sym_tree,&addr)); |
963 |
|
|
} |
964 |
|
|
|
965 |
|
|
/* Insert a new symbol */ |
966 |
|
|
struct symbol *mips64_sym_insert(cpu_mips_t *cpu,char *name,m_uint64_t addr) |
967 |
|
|
{ |
968 |
|
|
struct symbol *sym; |
969 |
|
|
size_t len; |
970 |
|
|
|
971 |
|
|
if (!cpu->sym_tree) |
972 |
|
|
return NULL; |
973 |
|
|
|
974 |
|
|
len = strlen(name); |
975 |
|
|
|
976 |
|
|
if (!(sym = malloc(len+1+sizeof(*sym)))) |
977 |
|
|
return NULL; |
978 |
|
|
|
979 |
|
|
memcpy(sym->name,name,len+1); |
980 |
|
|
sym->addr = addr; |
981 |
|
|
|
982 |
|
|
if (rbtree_insert(cpu->sym_tree,sym,sym) == -1) { |
983 |
|
|
free(sym); |
984 |
|
|
return NULL; |
985 |
|
|
} |
986 |
|
|
|
987 |
|
|
return sym; |
988 |
|
|
} |
989 |
|
|
|
990 |
|
|
/* Symbol comparison function */ |
991 |
|
|
static int mips64_sym_compare(m_uint64_t *a1,struct symbol *sym) |
992 |
|
|
{ |
993 |
|
|
if (*a1 > sym->addr) |
994 |
|
|
return(1); |
995 |
|
|
|
996 |
|
|
if (*a1 < sym->addr) |
997 |
|
|
return(-1); |
998 |
|
|
|
999 |
|
|
return(0); |
1000 |
|
|
} |
1001 |
|
|
|
1002 |
|
|
/* Create the symbol tree */ |
1003 |
|
|
int mips64_sym_create_tree(cpu_mips_t *cpu) |
1004 |
|
|
{ |
1005 |
|
|
cpu->sym_tree = rbtree_create((tree_fcompare)mips64_sym_compare,NULL); |
1006 |
|
|
return(cpu->sym_tree ? 0 : -1); |
1007 |
|
|
} |
1008 |
|
|
|
1009 |
|
|
/* Load a symbol file */ |
1010 |
|
|
int mips64_sym_load_file(cpu_mips_t *cpu,char *filename) |
1011 |
|
|
{ |
1012 |
|
|
char buffer[4096],func_name[128]; |
1013 |
|
|
m_uint64_t addr; |
1014 |
|
|
char sym_type; |
1015 |
|
|
FILE *fd; |
1016 |
|
|
|
1017 |
|
|
if (!cpu->sym_tree && (mips64_sym_create_tree(cpu) == -1)) { |
1018 |
|
|
fprintf(stderr,"CPU%u: Unable to create symbol tree.\n",cpu->id); |
1019 |
|
|
return(-1); |
1020 |
|
|
} |
1021 |
|
|
|
1022 |
|
|
if (!(fd = fopen(filename,"r"))) { |
1023 |
|
|
perror("load_sym_file: fopen"); |
1024 |
|
|
return(-1); |
1025 |
|
|
} |
1026 |
|
|
|
1027 |
|
|
while(!feof(fd)) { |
1028 |
|
|
fgets(buffer,sizeof(buffer),fd); |
1029 |
|
|
|
1030 |
|
|
if (sscanf(buffer,"%llx %c %s",&addr,&sym_type,func_name) == 3) { |
1031 |
|
|
mips64_sym_insert(cpu,func_name,addr); |
1032 |
|
|
} |
1033 |
|
|
} |
1034 |
|
|
|
1035 |
|
|
fclose(fd); |
1036 |
|
|
return(0); |
1037 |
|
|
} |