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dpavlin |
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/* |
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* Cisco 7200 (Predator) simulation platform. |
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* Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr) |
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*/ |
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#ifndef __MEMORY_H__ |
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#define __MEMORY_H__ |
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#include <sys/types.h> |
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#include "utils.h" |
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/* MTS operation */ |
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#define MTS_READ 0 |
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#define MTS_WRITE 1 |
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/* 0.5GB value */ |
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#define MTS_SIZE_512M 0x20000000 |
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/* MTS flag bits: D (device), ACC (memory access), C (chain) */ |
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#define MTS_FLAG_BITS 4 |
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#define MTS_FLAG_MASK 0x0000000fUL |
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/* Masks for MTS entries */ |
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#define MTS_CHAIN_MASK 0x00000001 |
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#define MTS_ACC_MASK 0x00000006 |
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#define MTS_DEV_MASK 0x00000008 |
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#define MTS_ADDR_MASK (~MTS_FLAG_MASK) |
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/* Device ID mask and shift, device offset mask */ |
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#define MTS_DEVID_MASK 0xfc000000 |
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#define MTS_DEVID_SHIFT 26 |
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#define MTS_DEVOFF_MASK 0x03fffff0 |
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/* Memory access flags */ |
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#define MTS_ACC_OK 0x00000000 /* Access OK */ |
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#define MTS_ACC_AE 0x00000002 /* Address Error */ |
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#define MTS_ACC_T 0x00000004 /* TLB Exception */ |
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#define MTS_ACC_U 0x00000006 /* Unexistent */ |
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/* Hash table size for MTS64 (default: [shift:16,bits:12]) */ |
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#define MTS64_HASH_SHIFT 15 |
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#define MTS64_HASH_BITS 15 |
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#define MTS64_HASH_SIZE (1 << MTS64_HASH_BITS) |
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#define MTS64_HASH_MASK (MTS64_HASH_SIZE - 1) |
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/* MTS64 hash on virtual addresses */ |
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#define MTS64_HASH(vaddr) (((vaddr) >> MTS64_HASH_SHIFT) & MTS64_HASH_MASK) |
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/* Hash table size for MTS32 (default: [shift:15,bits:15]) */ |
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#define MTS32_HASH_SHIFT 15 |
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#define MTS32_HASH_BITS 15 |
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#define MTS32_HASH_SIZE (1 << MTS32_HASH_BITS) |
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#define MTS32_HASH_MASK (MTS32_HASH_SIZE - 1) |
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/* MTS32 hash on virtual addresses */ |
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#define MTS32_HASH(vaddr) (((vaddr) >> MTS32_HASH_SHIFT) & MTS32_HASH_MASK) |
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/* Number of entries per chunk */ |
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#define MTS64_CHUNK_SIZE 256 |
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#define MTS32_CHUNK_SIZE 256 |
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/* MTS64: chunk definition */ |
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struct mts64_chunk { |
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mts64_entry_t entry[MTS64_CHUNK_SIZE]; |
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struct mts64_chunk *next; |
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u_int count; |
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}; |
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/* MTS32: chunk definition */ |
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struct mts32_chunk { |
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mts32_entry_t entry[MTS32_CHUNK_SIZE]; |
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struct mts32_chunk *next; |
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u_int count; |
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}; |
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/* Show the last memory accesses */ |
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void memlog_dump(cpu_mips_t *cpu); |
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/* Shutdown MTS subsystem */ |
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void mts_shutdown(cpu_mips_t *cpu); |
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/* Set the address mode */ |
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int mts_set_addr_mode(cpu_mips_t *cpu,u_int addr_mode); |
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/* Copy a memory block from VM physical RAM to real host */ |
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void physmem_copy_from_vm(vm_instance_t *vm,void *real_buffer, |
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m_uint64_t paddr,size_t len); |
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/* Copy a memory block to VM physical RAM from real host */ |
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void physmem_copy_to_vm(vm_instance_t *vm,void *real_buffer, |
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m_uint64_t paddr,size_t len); |
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/* Copy a 32-bit word from the VM physical RAM to real host */ |
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m_uint32_t physmem_copy_u32_from_vm(vm_instance_t *vm,m_uint64_t paddr); |
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/* Copy a 32-bit word to the VM physical RAM from real host */ |
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void physmem_copy_u32_to_vm(vm_instance_t *vm,m_uint64_t paddr,m_uint32_t val); |
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/* Copy a 16-bit word from the VM physical RAM to real host */ |
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m_uint16_t physmem_copy_u16_from_vm(vm_instance_t *vm,m_uint64_t paddr); |
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/* Copy a 16-bit word to the VM physical RAM from real host */ |
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void physmem_copy_u16_to_vm(vm_instance_t *vm,m_uint64_t paddr,m_uint16_t val); |
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/* DMA transfer operation */ |
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void physmem_dma_transfer(vm_instance_t *vm,m_uint64_t src,m_uint64_t dst, |
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size_t len); |
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/* strlen in VM physical memory */ |
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size_t physmem_strlen(vm_instance_t *vm,m_uint64_t paddr); |
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/* Physical memory dump (32-bit words) */ |
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void physmem_dump_vm(vm_instance_t *vm,m_uint64_t paddr,m_uint32_t u32_count); |
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#endif |
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