/[dynamips]/upstream/dynamips-0.2.6-RC3/dev_dec21140.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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upstream/dynamips-0.2.5/dev_dec21140.c revision 1 by dpavlin, Sat Oct 6 16:01:44 2007 UTC upstream/dynamips-0.2.6-RC3/dev_dec21140.c revision 4 by dpavlin, Sat Oct 6 16:06:49 2007 UTC
# Line 86  Line 86 
86  /* Maximum packet size */  /* Maximum packet size */
87  #define DEC21140_MAX_PKT_SIZE     2048  #define DEC21140_MAX_PKT_SIZE     2048
88    
89  /* Send up to 16 packets in a TX ring scan pass */  /* Send up to 32 packets in a TX ring scan pass */
90  #define DEC21140_TXRING_PASS_COUNT  16  #define DEC21140_TXRING_PASS_COUNT  32
91    
92  /* Setup frame size */  /* Setup frame size */
93  #define DEC21140_SETUP_FRAME_SIZE 192  #define DEC21140_SETUP_FRAME_SIZE 192
# Line 206  static inline int dec21140_handle_mac_ad Line 206  static inline int dec21140_handle_mac_ad
206     n_eth_hdr_t *hdr = (n_eth_hdr_t *)pkt;     n_eth_hdr_t *hdr = (n_eth_hdr_t *)pkt;
207     int i;     int i;
208    
    /* Ignore traffic sent by us */  
    for(i=0;i<d->mac_addr_count;i++)  
       if (!memcmp(&d->mac_addr[i],&hdr->saddr,N_ETH_ALEN))  
          return(FALSE);  
   
209     /* Accept systematically frames if we are running is promiscuous mode */     /* Accept systematically frames if we are running is promiscuous mode */
210     if (d->csr[6] & DEC21140_CSR6_PROMISC)     if (d->csr[6] & DEC21140_CSR6_PROMISC)
211        return(TRUE);        return(TRUE);
# Line 419  void *dev_dec21140_access(cpu_mips_t *cp Line 414  void *dev_dec21140_access(cpu_mips_t *cp
414  #if DEBUG_CSR_REGS  #if DEBUG_CSR_REGS
415        cpu_log(cpu,d->name,"read CSR%u value 0x%x\n",reg,d->csr[reg]);        cpu_log(cpu,d->name,"read CSR%u value 0x%x\n",reg,d->csr[reg]);
416  #endif  #endif
417          switch(reg) {
418        /* Dynamically construct CSR5 */           case 5:
419        if (reg == 5) {              /* Dynamically construct CSR5 */
420           *data = 0;              *data = 0;
421    
422           if (d->csr[6] & DEC21140_CSR6_START_RX)              if (d->csr[6] & DEC21140_CSR6_START_RX)
423              *data |= 0x03 << DEC21140_CSR5_RS_SHIFT;                 *data |= 0x03 << DEC21140_CSR5_RS_SHIFT;
424                  
425           if (d->csr[6] & DEC21140_CSR6_START_TX)              if (d->csr[6] & DEC21140_CSR6_START_TX)
426              *data |= 0x03 << DEC21140_CSR5_TS_SHIFT;                 *data |= 0x03 << DEC21140_CSR5_TS_SHIFT;
427                    
428           *data |= d->csr[5] & (DEC21140_CSR5_TI|DEC21140_CSR5_RI);              *data |= d->csr[5] & (DEC21140_CSR5_TI|DEC21140_CSR5_RI);
429        }              break;
       else  
          *data = d->csr[reg];  
430    
431        /* CSR8 is cleared when read */           case 8:
432        if (reg == 8)              /* CSR8 is cleared when read (missed frame counter) */
433           d->csr[reg] = 0;              d->csr[reg] = 0;
434                *data = 0;
435                break;
436                
437             default:
438                *data = d->csr[reg];
439          }
440     } else {     } else {
441  #if DEBUG_CSR_REGS  #if DEBUG_CSR_REGS
442        cpu_log(cpu,d->name,"write CSR%u value 0x%x\n",reg,(m_uint32_t)*data);        cpu_log(cpu,d->name,"write CSR%u value 0x%x\n",reg,(m_uint32_t)*data);
# Line 507  static m_uint32_t rxdesc_get_next(struct Line 506  static m_uint32_t rxdesc_get_next(struct
506     return(nrxd_addr);     return(nrxd_addr);
507  }  }
508    
509  /* Read an RX descriptor */  /* Read a RX descriptor */
510  static void rxdesc_read(struct dec21140_data *d,m_uint32_t rxd_addr,  static void rxdesc_read(struct dec21140_data *d,m_uint32_t rxd_addr,
511                          struct rx_desc *rxd)                          struct rx_desc *rxd)
512  {  {
# Line 675  static int dev_dec21140_handle_rxring(ne Line 674  static int dev_dec21140_handle_rxring(ne
674      * for this virtual machine.      * for this virtual machine.
675      */      */
676     if (dec21140_handle_mac_addr(d,pkt))     if (dec21140_handle_mac_addr(d,pkt))
677        dev_dec21140_receive_pkt(d,pkt,pkt_len);        return(dev_dec21140_receive_pkt(d,pkt,pkt_len));
678    
679     return(TRUE);     return(FALSE);
680  }  }
681    
682  /* Read a TX descriptor */  /* Read a TX descriptor */
# Line 726  static int dev_dec21140_handle_txring_si Line 725  static int dev_dec21140_handle_txring_si
725     /* Copy the current txring descriptor */     /* Copy the current txring descriptor */
726     tx_start = d->tx_current;       tx_start = d->tx_current;  
727     ptxd = &txd0;     ptxd = &txd0;
728     txdesc_read(d,d->tx_current,ptxd);     txdesc_read(d,tx_start,ptxd);
729    
730     /* If we don't own the first descriptor, we cannot transmit */     /* If we don't own the first descriptor, we cannot transmit */
731     if (!(txd0.tdes[0] & DEC21140_TXDESC_OWN))     if (!(txd0.tdes[0] & DEC21140_TXDESC_OWN))
# Line 939  struct dec21140_data *dev_dec21140_init( Line 938  struct dec21140_data *dev_dec21140_init(
938    
939     /* Basic register setup */     /* Basic register setup */
940     d->csr[0]   = 0xfff80000;     d->csr[0]   = 0xfff80000;
941       d->csr[5]   = 0xfc000000;
942     d->csr[8]   = 0xfffe0000;     d->csr[8]   = 0xfffe0000;
943    
944     dev->phys_addr = 0;     dev->phys_addr = 0;
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