86 |
/* Maximum packet size */ |
/* Maximum packet size */ |
87 |
#define DEC21140_MAX_PKT_SIZE 2048 |
#define DEC21140_MAX_PKT_SIZE 2048 |
88 |
|
|
89 |
/* Send up to 16 packets in a TX ring scan pass */ |
/* Send up to 32 packets in a TX ring scan pass */ |
90 |
#define DEC21140_TXRING_PASS_COUNT 16 |
#define DEC21140_TXRING_PASS_COUNT 32 |
91 |
|
|
92 |
/* Setup frame size */ |
/* Setup frame size */ |
93 |
#define DEC21140_SETUP_FRAME_SIZE 192 |
#define DEC21140_SETUP_FRAME_SIZE 192 |
419 |
#if DEBUG_CSR_REGS |
#if DEBUG_CSR_REGS |
420 |
cpu_log(cpu,d->name,"read CSR%u value 0x%x\n",reg,d->csr[reg]); |
cpu_log(cpu,d->name,"read CSR%u value 0x%x\n",reg,d->csr[reg]); |
421 |
#endif |
#endif |
422 |
|
switch(reg) { |
423 |
/* Dynamically construct CSR5 */ |
case 5: |
424 |
if (reg == 5) { |
/* Dynamically construct CSR5 */ |
425 |
*data = 0; |
*data = 0; |
426 |
|
|
427 |
if (d->csr[6] & DEC21140_CSR6_START_RX) |
if (d->csr[6] & DEC21140_CSR6_START_RX) |
428 |
*data |= 0x03 << DEC21140_CSR5_RS_SHIFT; |
*data |= 0x03 << DEC21140_CSR5_RS_SHIFT; |
429 |
|
|
430 |
if (d->csr[6] & DEC21140_CSR6_START_TX) |
if (d->csr[6] & DEC21140_CSR6_START_TX) |
431 |
*data |= 0x03 << DEC21140_CSR5_TS_SHIFT; |
*data |= 0x03 << DEC21140_CSR5_TS_SHIFT; |
432 |
|
|
433 |
*data |= d->csr[5] & (DEC21140_CSR5_TI|DEC21140_CSR5_RI); |
*data |= d->csr[5] & (DEC21140_CSR5_TI|DEC21140_CSR5_RI); |
434 |
} |
break; |
|
else |
|
|
*data = d->csr[reg]; |
|
435 |
|
|
436 |
/* CSR8 is cleared when read */ |
case 8: |
437 |
if (reg == 8) |
/* CSR8 is cleared when read */ |
438 |
d->csr[reg] = 0; |
d->csr[reg] = 0; |
439 |
|
break; |
440 |
|
|
441 |
|
default: |
442 |
|
*data = d->csr[reg]; |
443 |
|
} |
444 |
} else { |
} else { |
445 |
#if DEBUG_CSR_REGS |
#if DEBUG_CSR_REGS |
446 |
cpu_log(cpu,d->name,"write CSR%u value 0x%x\n",reg,(m_uint32_t)*data); |
cpu_log(cpu,d->name,"write CSR%u value 0x%x\n",reg,(m_uint32_t)*data); |
942 |
|
|
943 |
/* Basic register setup */ |
/* Basic register setup */ |
944 |
d->csr[0] = 0xfff80000; |
d->csr[0] = 0xfff80000; |
945 |
|
d->csr[5] = 0xfc000000; |
946 |
d->csr[8] = 0xfffe0000; |
d->csr[8] = 0xfffe0000; |
947 |
|
|
948 |
dev->phys_addr = 0; |
dev->phys_addr = 0; |