/[dynamips]/upstream/dynamips-0.2.6-RC3/dev_c7200_mpfpga.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Diff of /upstream/dynamips-0.2.6-RC3/dev_c7200_mpfpga.c

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upstream/dynamips-0.2.6-RC1/dev_c7200_mpfpga.c revision 2 by dpavlin, Sat Oct 6 16:03:58 2007 UTC upstream/dynamips-0.2.6-RC2/dev_c7200_mpfpga.c revision 3 by dpavlin, Sat Oct 6 16:05:34 2007 UTC
# Line 90  static const struct nmc93c46_eeprom_def Line 90  static const struct nmc93c46_eeprom_def
90     /* Bay 0 */     /* Bay 0 */
91     { BAY0_EEPROM_CLOCK_BIT , BAY0_EEPROM_SELECT_BIT,     { BAY0_EEPROM_CLOCK_BIT , BAY0_EEPROM_SELECT_BIT,
92       BAY0_EEPROM_DIN_BIT   , BAY0_EEPROM_DOUT_BIT,       BAY0_EEPROM_DIN_BIT   , BAY0_EEPROM_DOUT_BIT,
93       NULL, 0 },     },
94    
95     /* Bay 1 */     /* Bay 1 */
96     { BAY1_EEPROM_CLOCK_BIT , BAY1_EEPROM_SELECT_BIT,     { BAY1_EEPROM_CLOCK_BIT , BAY1_EEPROM_SELECT_BIT,
97       BAY1_EEPROM_DIN_BIT   , BAY1_EEPROM_DOUT_BIT,       BAY1_EEPROM_DIN_BIT   , BAY1_EEPROM_DOUT_BIT,
98       NULL, 0 },     },
99    
100     /* Bay 2 */     /* Bay 2 */
101     { BAY2_EEPROM_CLOCK_BIT , BAY2_EEPROM_SELECT_BIT,     { BAY2_EEPROM_CLOCK_BIT , BAY2_EEPROM_SELECT_BIT,
102       BAY2_EEPROM_DIN_BIT   , BAY2_EEPROM_DOUT_BIT,       BAY2_EEPROM_DIN_BIT   , BAY2_EEPROM_DOUT_BIT,
103       NULL, 0 },     },
104    
105     /* Bay 3 */     /* Bay 3 */
106     { BAY3_EEPROM_CLOCK_BIT , BAY3_EEPROM_SELECT_BIT,     { BAY3_EEPROM_CLOCK_BIT , BAY3_EEPROM_SELECT_BIT,
107       BAY3_EEPROM_DIN_BIT   , BAY3_EEPROM_DOUT_BIT,       BAY3_EEPROM_DIN_BIT   , BAY3_EEPROM_DOUT_BIT,
108       NULL, 0 },     },
109    
110     /* Bay 4 */     /* Bay 4 */
111     { BAY4_EEPROM_CLOCK_BIT , BAY4_EEPROM_SELECT_BIT,     { BAY4_EEPROM_CLOCK_BIT , BAY4_EEPROM_SELECT_BIT,
112       BAY4_EEPROM_DIN_BIT   , BAY4_EEPROM_DOUT_BIT,       BAY4_EEPROM_DIN_BIT   , BAY4_EEPROM_DOUT_BIT,
113       NULL, 0 },     },
114    
115     /* Bay 5 */     /* Bay 5 */
116     { BAY5_EEPROM_CLOCK_BIT , BAY5_EEPROM_SELECT_BIT,     { BAY5_EEPROM_CLOCK_BIT , BAY5_EEPROM_SELECT_BIT,
117       BAY5_EEPROM_DIN_BIT   , BAY5_EEPROM_DOUT_BIT,       BAY5_EEPROM_DIN_BIT   , BAY5_EEPROM_DOUT_BIT,
118       NULL, 0 },     },
119    
120     /* Bay 6 */     /* Bay 6 */
121     { BAY6_EEPROM_CLOCK_BIT , BAY6_EEPROM_SELECT_BIT,     { BAY6_EEPROM_CLOCK_BIT , BAY6_EEPROM_SELECT_BIT,
122       BAY6_EEPROM_DIN_BIT   , BAY6_EEPROM_DOUT_BIT,       BAY6_EEPROM_DIN_BIT   , BAY6_EEPROM_DOUT_BIT,
123       NULL, 0 },     },
124  };  };
125    
126  /* EEPROM group #1 (Bays 0, 1, 3, 4) */  /* EEPROM group #1 (Bays 0, 1, 3, 4) */
127  static const struct nmc93c46_group eeprom_bays_g1 = {  static const struct nmc93c46_group eeprom_bays_g1 = {
128     4, 0, "PA Bays (Group #1) EEPROM", FALSE,     4, 0, "PA Bays (Group #1) EEPROM", FALSE,
129    
130     { NULL, NULL, NULL, NULL },     { &eeprom_bay_def[0], &eeprom_bay_def[1],
131         &eeprom_bay_def[3], &eeprom_bay_def[4],
132     { { 0, 0, 0, 0, 0}, { 0, 0, 0, 0, 0}, { 0, 0, 0, 0, 0},     },
      { 0, 0, 0, 0, 0} },  
133  };  };
134    
135  /* EEPROM group #2 (Bays 2, 5, 6) */  /* EEPROM group #2 (Bays 2, 5, 6) */
136  static const struct nmc93c46_group eeprom_bays_g2 = {  static const struct nmc93c46_group eeprom_bays_g2 = {
137     3, 0, "PA Bays (Group #2) EEPROM", FALSE,     3, 0, "PA Bays (Group #2) EEPROM", FALSE,
   
    { NULL, NULL, NULL },  
138    
139     { { 0, 0, 0, 0, 0}, { 0, 0, 0, 0, 0}, { 0, 0, 0, 0, 0} },     { &eeprom_bay_def[2], &eeprom_bay_def[5], &eeprom_bay_def[6] },
140  };  };
141    
142  /* Midplane FPGA private data */  /* Midplane FPGA private data */
# Line 344  void *dev_c7200_mpfpga_access(cpu_mips_t Line 341  void *dev_c7200_mpfpga_access(cpu_mips_t
341  /* Initialize EEPROM groups */  /* Initialize EEPROM groups */
342  static void init_eeprom_groups(c7200_t *router)  static void init_eeprom_groups(c7200_t *router)
343  {  {
    struct nmc93c46_group *g;  
    int i;  
   
    for(i=0;i<C7200_MAX_PA_BAYS;i++) {  
       memcpy(&router->pa_bay[i].eeprom,&eeprom_bay_def[i],  
              sizeof(struct nmc93c46_eeprom_def));  
    }  
   
344     /* Group 1: bays 0, 1, 3, 4 */     /* Group 1: bays 0, 1, 3, 4 */
345     g = &router->pa_eeprom_g1;     router->pa_eeprom_g1 = eeprom_bays_g1;
346     memcpy(g,&eeprom_bays_g1,sizeof(struct nmc93c46_group));     router->pa_eeprom_g1.eeprom[0] = &router->pa_bay[0].eeprom;
347     g->def[0] = &router->pa_bay[0].eeprom;     router->pa_eeprom_g1.eeprom[1] = &router->pa_bay[1].eeprom;
348     g->def[1] = &router->pa_bay[1].eeprom;     router->pa_eeprom_g1.eeprom[2] = &router->pa_bay[3].eeprom;
349     g->def[2] = &router->pa_bay[3].eeprom;     router->pa_eeprom_g1.eeprom[3] = &router->pa_bay[4].eeprom;
    g->def[3] = &router->pa_bay[4].eeprom;  
350    
351     /* Group 2: bays 2, 5, 6 */     /* Group 2: bays 2, 5, 6 */
352     g = &router->pa_eeprom_g2;     router->pa_eeprom_g2 = eeprom_bays_g2;
353     memcpy(g,&eeprom_bays_g2,sizeof(struct nmc93c46_group));     router->pa_eeprom_g2.eeprom[0] = &router->pa_bay[2].eeprom;
354     g->def[0] = &router->pa_bay[2].eeprom;     router->pa_eeprom_g2.eeprom[1] = &router->pa_bay[5].eeprom;
355     g->def[1] = &router->pa_bay[5].eeprom;     router->pa_eeprom_g2.eeprom[2] = &router->pa_bay[6].eeprom;
    g->def[2] = &router->pa_bay[6].eeprom;  
   
    /* Set empty EEPROMs for all slots */  
    for(i=0;i<C7200_MAX_PA_BAYS;i++)  
       c7200_pa_unset_eeprom(router,i);  
356  }  }
357    
358  /* Shutdown the MP FPGA device */  /* Shutdown the MP FPGA device */

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