33 |
extern struct ppc32_insn_tag ppc32_insn_tags[]; |
extern struct ppc32_insn_tag ppc32_insn_tags[]; |
34 |
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|
35 |
/* Push epilog for an x86 instruction block */ |
/* Push epilog for an x86 instruction block */ |
36 |
static forced_inline void ppc32_jit_tcb_push_epilog(ppc32_jit_tcb_t *block) |
static forced_inline void ppc32_jit_tcb_push_epilog(u_char **ptr) |
37 |
{ |
{ |
38 |
amd64_ret(block->jit_ptr); |
amd64_ret(*ptr); |
39 |
} |
} |
40 |
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|
41 |
/* Execute JIT code */ |
/* Execute JIT code */ |
48 |
offset = (cpu->ia & PPC32_MIN_PAGE_IMASK) >> 2; |
offset = (cpu->ia & PPC32_MIN_PAGE_IMASK) >> 2; |
49 |
jit_code = (insn_tblock_fptr)block->jit_insn_ptr[offset]; |
jit_code = (insn_tblock_fptr)block->jit_insn_ptr[offset]; |
50 |
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#if 0 |
|
51 |
if (unlikely(!jit_code)) { |
if (unlikely(!jit_code)) { |
52 |
ppc32_exec_single_step(cpu,vmtoh32(block->ppc_code[offset])); |
ppc32_jit_tcb_set_target_bit(block,cpu->ia); |
53 |
return; |
|
54 |
|
if (++block->target_undef_cnt == 16) { |
55 |
|
ppc32_jit_tcb_recompile(cpu,block); |
56 |
|
jit_code = (insn_tblock_fptr)block->jit_insn_ptr[offset]; |
57 |
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} else { |
58 |
|
ppc32_exec_page(cpu); |
59 |
|
return; |
60 |
|
} |
61 |
} |
} |
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#endif |
|
62 |
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63 |
asm volatile ("movq %0,%%r15"::"r"(cpu): |
asm volatile ("movq %0,%%r15"::"r"(cpu): |
64 |
"r14","r15","rax","rbx","rcx","rdx","rdi","rsi"); |
"r13","r14","r15","rax","rbx","rcx","rdx","rdi","rsi"); |
65 |
jit_code(); |
jit_code(); |
66 |
} |
} |
67 |
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|
87 |
x86_patch(code,target); |
x86_patch(code,target); |
88 |
} |
} |
89 |
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|
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/* Set the Instruction Address (IA) register */ |
|
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void ppc32_set_ia(ppc32_jit_tcb_t *b,m_uint32_t new_ia); |
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/* Set the Link Register (LR) */ |
|
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void ppc32_set_lr(ppc32_jit_tcb_t *b,m_uint32_t new_lr); |
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|
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/* Increment the number of executed instructions (performance debugging) */ |
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void ppc32_inc_perf_counter(ppc32_jit_tcb_t *b); |
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90 |
#endif |
#endif |